CY14B256K

 

 

 

 

 

 

 

 

 

Hardware STORE Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

Alt.

 

 

Description

 

CY14B256K

 

Unit

Parameter

 

 

Min

 

Max

 

tDELAY [22]

 

Time Allowed to Complete SRAM Cycle

1

 

70

 

μs

tPHSB

tHLHX

Hardware STORE Pulse Width

15

 

 

 

ns

Figure 15. Hardware STORE Cycle

+6% ,1

+6% 287

W3+6%+/+;

W+/%/

W6725(

+,*+,03('$1&(

+,*+,03('$1&(

W'(/$<

'4 '$7$287 '$7$9$/,'

'$7$9$/,'

Soft Sequence Commands

Parameter

Description

 

CY14B256K

Unit

Min

 

Max

 

 

 

 

tSS [23, 24]

Soft Sequence Processing Time

 

 

70

μs

Figure 16. Soft Sequence Processing [23, 24]

 

6RIW6HTXHQFH

W66

6RIW6HTXHQFH

W66

 

&RPPDQG

 

 

&RPPDQG

 

 

$GGUHVV

$GGUHVV

$GGUHVV

$GGUHVV

$GGUHVV

 

 

W6$

 

W&:

 

W&:

 

&(

 

 

 

 

 

 

9&&

 

 

 

 

 

 

Notes

22.Read and Write cycles in progress before HSB are given this amount of time to complete.

23.This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

24.Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See specific command.

Document Number: 001-06431 Rev. *H

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Cypress CY14B256K manual Hardware Store Cycle, Soft Sequence Commands