CY14B256K

AC Switching Characteristics

Parameter

Description

25 ns

35 ns

45 ns

Unit

Cypress

Alt.

Min

Max

Min

Max

Min

Max

Parameter

Parameter

 

 

 

 

 

 

 

 

 

 

SRAM Read

Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tACE

tELQV

Chip Enable Access Time

 

25

 

35

 

45

ns

tRC [10]

tAVAV, tELEH

Read Cycle Time

25

 

35

 

45

 

ns

tAA [11]

tAVQV

Address Access Time

 

25

 

35

 

45

ns

tDOE

tGLQV

Output Enable to Data Valid

 

12

 

15

 

20

ns

tOHA [11]

tAXQX

Output Hold After Address Change

3

 

3

 

3

 

ns

tLZCE [12]

tELQX

Chip Enable to Output Active

3

 

3

 

3

 

ns

tHZCE [12]

tEHQZ

Chip Disable to Output Inactive

 

10

 

13

 

15

ns

tLZOE [12]

tGLQX

Output Enable to Output Active

0

 

0

 

0

 

ns

tHZOE [12]

tGHQZ

Output Disable to Output Inactive

 

10

 

13

 

15

ns

tPU [13]

tELICCH

Chip Enable to Power Active

0

 

0

 

0

 

ns

tPD [13]

tEHICCL

Chip Disable to Power Standby

 

25

 

35

 

45

ns

Figure 8. SRAM Read Cycle 1: Address Controlled [10, 11, 14]

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W5&

W$$

W2+$

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Figure 9. SRAM Read Cycle 2: CE and OE Controlled [10, 14]

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&(

2(

'4 '$7$287

,&&

W5&

W$&(

W/=&(

W'2(

W/=2(

W38 $&7,9(

67$1'%<

W3'

W+=&(

W+=2(

'$7$9$/,'

Notes

10.WE is HIGH during SRAM Read Cycles.

11.Device is continuously selected with CE and OE both Low.

12.Measured ±200 mV from steady state output voltage.

13.These parameters are guaranteed by design and are not tested.

14.HSB must remain HIGH during READ and WRITE cycles.

Document Number: 001-06431 Rev. *H

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Cypress CY14B256K manual AC Switching Characteristics, Parameter Sram Read Cycle