CY14B256K
256 Kbit (32K x 8) nvSRAM with Real Time Clock
Features
■25 ns, 35 ns, and 45 ns access times
■Pin compatible with STK17T88
■Data integrity of Cypress nvSRAM combined with full featured Real Time Clock
❐Low power, 350 nA RTC current
❐Capacitor or battery backup for RTC
■Watchdog timer
■Clock alarm with programmable interrupts
■Hands off automatic STORE on power down with only a small capacitor
■STORE to QuantumTrap™ initiated by software, device pin, or on power down
■RECALL to SRAM initiated by software or on power up
■Infinite READ, WRITE, and RECALL cycles
■High reliability
❐Endurance to 200K cycles
❐Data retention: 20 years at 55°C
■Single 3V operation with tolerance of +20%,
■Commercial and industrial temperature
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Functional Description
The Cypress CY14B256K combines a 256 Kbit nonvolatile static RAM with a
The real time clock function provides an accurate clock with leap year tracking and a programmable high accuracy oscillator. The alarm function is programmable for one time alarms or periodic seconds, minutes, hours, or days. There is also a programmable watchdog timer for process control.
Logic Block Diagram
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| QuantumTrap | VCC | VCAP |
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| 512 X 512 | POWER | VRTCbat |
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A5 | DECODER | STORE | CONTROL | VRTCcap |
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A6 |
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A7 | RECALL | STORE/ |
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A8 |
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STATIC RAM | RECALL |
| HSB | |||
A9 | ARRAY |
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CONTROL |
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A11 | ROW | 512 X 512 |
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A12 |
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A13 |
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| SOFTWARE | A13 - A0 | |
A14 |
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| DETECT | |||
DQ0 |
| COLUMN IO |
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DQ1 | BUFFERS | COLUMN DEC |
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DQ2 |
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| x1 | ||
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DQ3 |
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| RTC |
| x2 | |
DQ4 |
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| INT | |
INPUT |
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DQ5 | A0 A1 A2 A3 A4 A10 |
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DQ6 |
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DQ7 |
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| MUX |
| A14 - A0 |
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| OE |
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| CE |
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| WE |
Cypress Semiconductor Corporation • 198 Champion Court | • | San Jose, CA | • | |
Document Number: |
| Revised February 24, 2009 |
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