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| CY14B256K |
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Table 4. Register Map Detail (continued) |
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| Alarm - Hours |
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0x7FF4 |
| D7 |
| D6 |
| D5 |
| D4 |
| D3 |
| D2 |
| D1 | D0 |
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| M |
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| 10s Alarm Hours |
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| Alarm Hours |
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| Contains the alarm value for the hours and the mask bit to select or deselect the hours value. |
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M | Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1 causes the match circuit |
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| to ignore the hours value. |
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| Alarm - Minutes |
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0x7FF3 |
| D7 |
| D6 |
| D5 |
| D4 |
| D3 |
| D2 |
| D1 | D0 |
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| Alarm Minutes |
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| Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value. |
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M | Match. When this bit is set to 0, the minutes value is used in the alarm match. Setting this bit to 1 causes the match |
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| circuit to ignore the minutes value. |
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| Alarm - Seconds |
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0x7FF2 |
| D7 |
| D6 |
| D5 |
| D4 |
| D3 |
| D2 |
| D1 | D0 |
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| Alarm Seconds |
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| Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value. |
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M | Match. When this bit is set to 0, the seconds value is used in the alarm match. Setting this bit to 1 causes the match |
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| Time Keeping - Centuries |
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| D7 |
| D6 |
| D5 |
| D4 |
| D3 |
| D2 |
| D1 | D0 |
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0x7FF1 |
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| 10s Centuries |
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| Centuries |
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| Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains |
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| Flags |
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0x7FF0 |
| D7 |
| D6 |
| D5 |
| D4 |
| D3 |
| D2 |
| D1 | D0 |
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| WDF |
| AF |
| PF |
| OSCF |
| 0 |
| CAL |
| W | R |
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WDF | Watchdog Timer Flag. This read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset |
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AF | Alarm Flag. This read only bit is set to 1 when the time and date match the values stored in the alarm registers with the |
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PF | Power Fail Flag. This read only bit is set to 1 when power falls below the power fail threshold VSWITCH. It is cleared to |
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OSCF | Oscillator Fail Flag. Set to 1 on power up if the oscillator is enabled and not running in the first 5 ms of operation. This |
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| indicates that RTC backup power failed and clock value is no longer valid. The user must reset this bit to 0 to clear this |
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| condition (Flag). The chip does not clear this flag. This bit survives power cycles. |
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CAL | Calibration Mode. When set to 1, a 512 Hz square wave is output on the INT pin. When set to 0, the INT pin resumes |
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W | Write Enable: Setting the W bit to 1 freezes updatesof the RTC registers. The user can then write to RTC registers, Alarm |
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| registers, Calibration register, Interrupt register and Flags register. Setting the W bit to 0 causes the contents of the RTC |
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| registers to be transferred to the time keeping counters if the time has been changed (a new base time is loaded). This |
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| bit defaults to 0 on power up. |
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RRead Enable: Setting R bit to 1, stops clock updates to user RTC registers so that clock updates are not seen during the reading process. Set R bit to 0 to resume clock updates to the holding register. Setting this bit does not require W bit to be set to 1. This bit defaults to 0 on power up.
Document Number: | Page 14 of 28 |
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