Cypress CY62167E MoBL manual Switching Characteristics, Parameter Description 45 ns Unit Min Max

CY62167E MoBL®

Switching Characteristics

Over the Operating Range[13, 14]

Parameter					Description		45 ns		Unit
						Min		Max
READ CYCLE
tRC		Read Cycle Time				45			ns
tAA		Address to Data Valid						45	ns
tOHA		Data Hold from Address Change				10			ns
tACE			1 LOW and CE2 HIGH to Data Valid					45	ns
		CE
tDOE				LOW to Data Valid				22	ns
		OE
tLZOE				LOW to LOW-Z[15]		5			ns
		OE
tHZOE				HIGH to High-Z[15, 16]				18	ns
		OE
tLZCE			1 LOW and CE2 HIGH to Low-Z[15]			10			ns
		CE
tHZCE			1 HIGH and CE2 LOW to High-Z[15, 16]					18	ns
		CE
tPU			1 LOW and CE2 HIGH to Power Up			0			ns
		CE
tPD			1 HIGH and CE2 LOW to Power Down					45	ns
		CE
tDBE		BLE/BHE LOW to Data Valid						45	ns
tLZBE						10			ns
		BLE/BHE LOW to Low-Z[15]
t								18	ns
		BLE/BHE HIGH to HIGH-Z[15, 16]
HZBE
WRITE CYCLE	[17]
tWC		Write Cycle Time				45			ns
tSCE			1 LOW and CE2 HIGH to Write End			35			ns
		CE
tAW		Address Setup to Write End				35			ns
tHA		Address Hold from Write End				0			ns
tSA		Address Setup to Write Start				0			ns
tPWE				Pulse Width		35			ns
		WE
tBW						35			ns
		BLE/BHE LOW to Write End
tSD		Data Setup to Write End				25			ns
tHD		Data Hold from Write End				0			ns
tHZWE				LOW to High-Z[15, 16]				18	ns
		WE
t				HIGH to Low-Z[15]		10			ns
		WE
LZWE

Notes

13.Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4.

14.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.

15.At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.

16.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.

17.The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.

Document #: 001-15607 Rev. *A Page 5 of 12

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