Cypress CY62167E MoBL CY62167E MoBL

CY62167E MoBL®

PREVIOUS DATA VALID DATA VALID

tAA

tOHA

tRC

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE

tPD

tHZBE

tLZBE

HZCE

tDBE

CE1

ADDRESS

CE2

BHE/BLE

DATA OUT

VCC

SUPPLY

CURRENT

HIGH

ICC

ISB

IMPEDANCE

Notes

18.The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH.

19.WE is HIGH for read cycle.

20.Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.

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Contents

Main 16-Mbit (1M x 16 / 2M x 8) Static RAM CY62167E MoBL Features Functional Description Logic Block Diagram CY62167E MoBL Document #: 001-15607 Rev. *A Page 2 of 12 Pin Configuration 48-Pin TSOP I Product Portfolio Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform Switching Characteristics CY62167E MoBL Document #: 001-15607 Rev. *A Page 6 of 12 Switching Waveforms Figure 2 shows OE controlled read cycle waveforms.[19, 20] Figure 2. Read Cycle No. 2 CY62167E MoBL Document #: 001-15607 Rev. *A Page 7 of 12 Figure 3 shows WE controlled write cycle waveforms.[17, 21, 22] Figure 3. Write Cycle No. 1 Figure 4 shows CE1 or CE2 controlled write cycle waveforms.[17, 21, 22] Figure 4. Write Cycle No. 2 Figure 5 shows WE controlled, OE LOW write cycle waveforms.[22] Figure 5. Write Cycle No. 3 t Figure 6 shows BHE/BLE controlled, OE LOW write cycle waveforms.[22] Figure 6. Write Cycle No. 4 Truth Table Ordering Information Package Diagram Figure 7. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183 Document History Page