Cypress CY62167E MoBL manual Features, Functional Description1, Logic Block Diagram

CY62167E MoBL®

16-Mbit (1M x 16 / 2M x 8) Static RAM

Features

•Configurable as 1M x 16 or as 2M x 8 SRAM

•Very high speed: 45 ns

•Wide voltage range: 4.5V–5.5V

•Ultra low standby power

—Typical standby current: 1.5 ∝A

—Maximum standby current: 12 ∝A

•Ultra low active power

—Typical active current: 2.2 mA @ f = 1 MHz

•Easy memory expansion with CE1, CE2, and OE features

•Automatic power down when deselected

•CMOS for optimum speed and power

•Offered in 48-pin TSOP I package

Functional Description[1]

The CY62167E is a high performance CMOS static RAM organized as 1M words by 16 bits/2M words by 8 bits. This device features advanced circuit design to provide an ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption by 99% when addresses are not toggling. Place the device into standby mode when deselected

(CE1 HIGH, or CE2 LOW, or both BHE and BLE are HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when:

•The device is deselected (CE1 HIGH or CE2 LOW)

•Outputs are disabled (OE HIGH)

•Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or

•A write operation is in progress (CE1 LOW, CE2 HIGH, and

WE LOW)

To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from the IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A19).

To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the “Truth Table” on page 10 for a complete description of read and write modes.

Logic Block Diagram

		DATA IN DRIVERS
A10
A 9
A 8	ROW DECODER
A 7
A 6		1M × 16 / 2M x 8		IO0–IO7
A 5		RAM ARRAY
A 4				IO8–IO15
A 3
A 2				AMPSSENSE
A 1
A 0
		COLUMN DECODER
				BYTE
	CE2			BHE
POWER DOWN	CE1	11 12 13 14 15 16 17 18	19	WE	CE2
		A A A A A A A A A		OE	CE1
CIRCUIT	BHE
	BLE			BLE

Note

1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

Cypress Semiconductor Corporation	• 198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 001-15607 Rev. *A	Revised June 07, 2007

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