CY7C1141V18, CY7C1156V18
CY7C1143V18, CY7C1145V18
Document Number: 001-06583 Rev. *D Page 22 of 28
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 1.8V
VDDQ = 1.5V
5pF
CCLK Clock Input Capacitance 6 pF
COOutput Capacitance 7pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter Description Test Conditions 165 FBGA
Package Unit
ΘJA Thermal Resistance
(junction to ambient) Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
13.48 °C/W
ΘJC Thermal Resistance
(junction to case) 4.15 °C/W
AC Test Loads and Waveforms
Figure 6. AC Test Loads and Waveforms
1.25V
0.25V
R = 50
Ω
5pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
Device R
L
= 50
Ω
Z
0
= 50
Ω
V
REF
= 0.75V
V
REF
= 0.75V
[22]
0.75V
Under
Test
0.75V
Device
Under
Test
OUTPUT
0.75V
V
REF
V
REF
OUTPUT

ZQ

ZQ

(a)
Slew Rate = 2 V/ns
RQ =
250
Ω
(b)
RQ =
250
Ω
Notes
22.Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
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