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Cypress CY7C1145V18, CY7C1143V18 Pin Configurations, CY7C1141V18 2M x, CY7C1156V18 2M x, NC/144M

Models: CY7C1156V18 CY7C1145V18 CY7C1143V18 CY7C1141V18

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CY7C1141V18, CY7C1156V18

CY7C1143V18, CY7C1145V18

Pin Configurations

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1141V18 (2M x 8)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

NC/144M

A

NC/36M

CQ

WPS

NWS

1

K

RPS

B

NC

A

NC/288M

K

0

A

NC

Q3

NWS

C

NC

VSS

A

NC

A

VSS

NC

D3

D

NC

D4

NC

VSS

NC

E

NC

Q4

VDDQ

VSS

VDDQ

NC

D2

Q2

F

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

G

NC

D5

Q5

VDDQ

VDD

VSS

VDD

VDDQ

NC

H

VREF

VDDQ

VDD

VSS

VDD

VDDQ

VREF

ZQ

DOFF

J

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q1

D1

K

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

L

NC

Q6

D6

VDDQ

VSS

VDDQ

NC

Q0

M

NC

VSS

NC

D0

N

NC

D7

NC

VSS

A

VSS

NC

P

NC

Q7

A

QVLD

A

NC

R

TDO

TCK

A

NC

A

TMS

TDI

CY7C1156V18 (2M x 9)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

NC

NC/144M

A

NC/36M

CQ

WPS

K

RPS

B

NC

A

NC/288M

K

0

A

NC

Q4

BWS

C

NC

VSS

A

NC

A

VSS

NC

D4

D

NC

D5

NC

VSS

NC

E

NC

Q5

VDDQ

VSS

VDDQ

NC

D3

Q3

F

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

G

NC

D6

Q6

VDDQ

VDD

VSS

VDD

VDDQ

NC

H

VREF

VDDQ

VDD

VSS

VDD

VDDQ

VREF

ZQ

DOFF

J

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q2

D2

K

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

L

NC

Q7

D7

VDDQ

VSS

VDDQ

NC

Q1

M

NC

VSS

NC

D1

N

NC

D8

NC

VSS

A

VSS

NC

P

NC

Q8

A

QVLD

A

NC

D0

Q0

R

TDO

TCK

A

NC

A

TMS

TDI

Document Number: 001-06583 Rev. *D

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Cypress CY7C1145V18, CY7C1143V18 manual Pin Configurations, CY7C1141V18 2M x, CY7C1156V18 2M x, NC/144M

Contents

Features ConfigurationsFunctional Description Selection Guide Logic Block Diagram CY7C1141V18 Logic Block Diagram CY7C1156V18 Logic Block Diagram CY7C1143V18 Logic Block Diagram CY7C1145V18 Pin Configurations CY7C1141V18 2M xCY7C1156V18 2M x NC/144M CY7C1143V18 1M x CY7C1145V18 512K xWPS BWS WPS BWS RPS Pin Definitions Pin Name Pin DescriptionBWS2, BWS3 Qvld Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for Jtag Functional Overview Read OperationsWrite Operations Byte Write Operations Valid Data Indicator Qvld Depth ExpansionProgrammable Impedance Echo Clocks Application Example Sram #4BUS Master Operation Write Cycle Descriptions CommentsRemains unaltered During the data portion of a write sequence Write cycle descriptions of CY7C1145V18 follows.2 DeviceInto the device. D359 remains unaltered Device. D80 and D3518 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Tap Controller State Diagram11 TAP Controller Block Diagram TAP Electrical CharacteristicsTAP Controller Parameter Description Test Conditions Min Max Unit TAP AC Switching Characteristics TAP Timing and Test Condition Scan Register Sizes Identification Register DefinitionsInstruction Codes Boundary Scan Order Bit # Bump ID Power Up Sequence in QDR-II+ Sram Power Up SequencePower Up Waveforms DLL Constraints Electrical Characteristics AC Electrical CharacteristicsMaximum Ratings Operating Range Capacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max Unit Switching Characteristics Cypress Consortium Description 375 MHz 333 MHz 300 MHz UnitParameter Min Max DLL Timing Switching Waveforms Read/Write/Deselect Sequence Waveform for 2.0 Cycle Read Latency 30, 31 Diagram Ordering InformationSpeed Ordering Code Package Package Type Operating CY7C1156V18-375BZXI CY7C1143V18-375BZXI CY7C1145V18-375BZXI 300 Package Diagram Ball Fbga 13 x 15 x 1.4 mm ECN No Issue Date Orig. Description of Change Document HistoryVKN/KKVTMP VKN/AESA