CY7C1141V18, CY7C1156V18CY7C1143V18, CY7C1145V18
Document Number: 001-06583 Rev. *D Page 7 of 28
CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
clock (K) of the QDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”
on page23.
ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, connect this pin directly to VDDQ, which enables
the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF Input DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned off operationis different from those listed in this data sheet. For normal
operation, connect this pin to a pull up through a 10 KΩ or less pull up resistor. The device behaves
in QDR-I mode when the DLL is turned off. In this mode, operate the device at a frequency of up to
167 MHz with QDR-I timing.
TDO Output TDO for JTAG.
TCK Input TCK Pin for JTAG.
TDI Input TDI Pin for JTAG.
TMS Input TMS Pin for JTAG.
NC N/A Not Connected to the Die. Tie to any voltage level.
NC/36M N/A Not Connected to the Die. Tie to any voltage level.
NC/72M N/A Not Connected to the Die. Tie to any voltage level.
NC/144M N/A Not Connected to the Die. Tie to any voltage level.
NC/288M N/A Not Connected to the Die. Tie to any voltage level.
VREF Input-
Reference Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and
AC measurement points.
VDD Power Supply Power Supply Inputs to the Core of the Device.
VSS Ground Ground for the Device.
VDDQ Power Supply Power Supply Inputs for the Outputs of the Device.
Pin Definitions (continued)
Pin Name IO Pin Description
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