300 | Cypress CY7C1143V18, CY7C1145V18, CY7C1141V18, CY7C1156V18

CY7C1141V18, CY7C1156V18

CY7C1143V18, CY7C1145V18

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
300	CY7C1141V18-300BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1156V18-300BZC

	CY7C1143V18-300BZC

	CY7C1145V18-300BZC

	CY7C1141V18-300BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1156V18-300BZXC

	CY7C1143V18-300BZXC

	CY7C1145V18-300BZXC

	CY7C1141V18-300BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1156V18-300BZI

	CY7C1143V18-300BZI

	CY7C1145V18-300BZI

	CY7C1141V18-300BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1156V18-300BZXI

	CY7C1143V18-300BZXI

	CY7C1145V18-300BZXI

Document Number: 001-06583 Rev. *D

Page 26 of 28

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Cypress CY7C1143V18, CY7C1145V18, CY7C1141V18, CY7C1156V18 manual 300

Contents

Functional Description FeaturesConfigurations Selection Guide Logic Block Diagram CY7C1141V18 Logic Block Diagram CY7C1156V18 Logic Block Diagram CY7C1143V18 Logic Block Diagram CY7C1145V18 CY7C1156V18 2M x Pin ConfigurationsCY7C1141V18 2M x NC/144M WPS BWS CY7C1143V18 1M xCY7C1145V18 512K x WPS BWS RPS BWS2, BWS3 Pin DefinitionsPin Name Pin Description Qvld TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for Jtag Write Operations Functional OverviewRead Operations Byte Write Operations Programmable Impedance Valid Data Indicator QvldDepth Expansion Echo Clocks BUS Master Application ExampleSram #4 Operation Remains unaltered Write Cycle DescriptionsComments During the data portion of a write sequence Into the device. D359 remains unaltered Write cycle descriptions of CY7C1145V18 follows.2Device Device. D80 and D3518 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Tap Controller State Diagram11 TAP Controller TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max Unit TAP AC Switching Characteristics TAP Timing and Test Condition Instruction Codes Identification Register DefinitionsScan Register Sizes Boundary Scan Order Bit # Bump ID Power Up Waveforms Power Up Sequence in QDR-II+ SramPower Up Sequence DLL Constraints Maximum Ratings Electrical CharacteristicsAC Electrical Characteristics Operating Range AC Test Loads and Waveforms CapacitanceThermal Resistance Parameter Description Test Conditions Max Unit Parameter Min Max Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit DLL Timing Switching Waveforms Read/Write/Deselect Sequence Waveform for 2.0 Cycle Read Latency 30, 31 Speed Ordering Code Package Package Type Operating DiagramOrdering Information CY7C1156V18-375BZXI CY7C1143V18-375BZXI CY7C1145V18-375BZXI 300 Package Diagram Ball Fbga 13 x 15 x 1.4 mm VKN/KKVTMP ECN No Issue Date Orig. Description of ChangeDocument History VKN/AESA