CY7C1141V18, CY7C1156V18

CY7C1143V18, CY7C1145V18

Switching Waveforms

Read/Write/Deselect Sequence

Figure 7. Waveform for 2.0 Cycle Read Latency [30, 31, 32]

NOP

READ

WRITE

READ

WRITE

NOP

 

 

1

2

3

4

5

6

7

8

K

tKH

tKL tCYC tKHKH

K

RPS

 

tSC tHC

t SC tHC

WPS

A

D

QVLD

A0

A1

A2

 

A3

 

 

 

 

 

tSA tHA

t

HD

 

tSD

tHD

 

 

 

t SD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D10

D11

D12

D13

D30

D31

D32

D33

 

tQVLD

 

 

 

 

 

 

 

 

 

 

 

tCO

 

tDOH

 

 

tCQDOH

 

 

 

tCLZ

 

 

tCQD

 

 

 

 

 

 

 

 

 

 

tQVLD

tCHZ

Q

CQ

CQ

Q00Q01Q02 Q03Q20

(Read Latency = 2.0 Cycles)

 

t

tCQOH

CCQO

 

 

 

tCQH tCQHCQH

 

t

CCQO

tCQOH

 

 

 

Q21 Q22Q23

DON’T CARE

UNDEFINED

Notes

30.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.

31.Outputs are disabled (High-Z) one clock cycle after a NOP.

32.In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Document Number: 001-06583 Rev. *D

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Cypress CY7C1145V18 manual Switching Waveforms Read/Write/Deselect Sequence, Waveform for 2.0 Cycle Read Latency 30, 31