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Cypress CY7C1145V18, CY7C1141V18, CY7C1143V18 Switching Waveforms Read/Write/Deselect Sequence

Models: CY7C1156V18 CY7C1145V18 CY7C1143V18 CY7C1141V18

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CY7C1141V18, CY7C1156V18

CY7C1143V18, CY7C1145V18

Switching Waveforms

Read/Write/Deselect Sequence

Figure 7. Waveform for 2.0 Cycle Read Latency [30, 31, 32]

NOP	READ	WRITE	READ	WRITE	NOP
1	2	3	4	5	6	7	8

tKH

tKL tCYC tKHKH

RPS
tSC tHC	t SC tHC

WPS

QVLD

A0	A1	A2		A3
tSA tHA	t	HD		tSD		tHD
tSA tHA	t SD	HD		tSD
	t SD
		D10	D11	D12	D13	D30	D31	D32	D33
	tQVLD
			tCO		tDOH			tCQDOH
		tCLZ	tCO			tCQD		tCQDOH
		tCLZ				tCQD

tQVLD

tCHZ

Q00Q01Q02 Q03Q20

(Read Latency = 2.0 Cycles)			t
		tCQOH	CCQO

tCQH tCQHCQH		t	CCQO
	tCQOH

Q21 Q22Q23

DON’T CARE

UNDEFINED

Notes

30.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.

31.Outputs are disabled (High-Z) one clock cycle after a NOP.

32.In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Document Number: 001-06583 Rev. *D

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Cypress CY7C1145V18 manual Switching Waveforms Read/Write/Deselect Sequence, Waveform for 2.0 Cycle Read Latency 30, 31

Contents

Features ConfigurationsFunctional Description Selection Guide Logic Block Diagram CY7C1141V18 Logic Block Diagram CY7C1156V18 Logic Block Diagram CY7C1143V18 Logic Block Diagram CY7C1145V18 Pin Configurations CY7C1141V18 2M xCY7C1156V18 2M x NC/144M CY7C1143V18 1M x CY7C1145V18 512K xWPS BWS WPS BWS RPS Pin Definitions Pin Name Pin DescriptionBWS2, BWS3 Qvld Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for Jtag Functional Overview Read OperationsWrite Operations Byte Write Operations Valid Data Indicator Qvld Depth ExpansionProgrammable Impedance Echo Clocks Application Example Sram #4BUS Master Operation Write Cycle Descriptions CommentsRemains unaltered During the data portion of a write sequence Write cycle descriptions of CY7C1145V18 follows.2 DeviceInto the device. D359 remains unaltered Device. D80 and D3518 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram Tap Controller State Diagram11 TAP Controller Block Diagram TAP Electrical CharacteristicsTAP Controller Parameter Description Test Conditions Min Max Unit TAP AC Switching Characteristics TAP Timing and Test Condition Identification Register Definitions Scan Register SizesInstruction Codes Boundary Scan Order Bit # Bump ID Power Up Sequence in QDR-II+ Sram Power Up SequencePower Up Waveforms DLL Constraints Electrical Characteristics AC Electrical CharacteristicsMaximum Ratings Operating Range Capacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max Unit Switching Characteristics Cypress Consortium Description 375 MHz 333 MHz 300 MHz UnitParameter Min Max DLL Timing Switching Waveforms Read/Write/Deselect Sequence Waveform for 2.0 Cycle Read Latency 30, 31 Diagram Ordering InformationSpeed Ordering Code Package Package Type Operating CY7C1156V18-375BZXI CY7C1143V18-375BZXI CY7C1145V18-375BZXI 300 Package Diagram Ball Fbga 13 x 15 x 1.4 mm ECN No Issue Date Orig. Description of Change Document HistoryVKN/KKVTMP VKN/AESA