Cypress CY7C1143V18, CY7C1145V18, CY7C1141V18 Application Example, Sram #4, BUS Master, Operation

CY7C1141V18, CY7C1156V18

CY7C1143V18, CY7C1145V18

Application Example

Figure 1 shows the four QDR-II+ used in an application.

Figure 1. Appliation Example

			SRAM #1		ZQ	RQ = 250ohms			ZQ	RQ = 250ohms
	Vt			CQ/CQ				SRAM #4	CQ/CQ
		D			Q		D		Q
	R	A	RPS WPS BWS	K	K		A	RPS WPS BWS	K K
DATA IN								R
DATA OUT
								Vt
Address								Vt
BUS MASTER	RPS							R
(CPU or ASIC)	WPS
	BWS
CLKIN/CLKIN
Source K
Source K								R = 50ohms, Vt = VDDQ/2

Truth Table

The truth table for the CY7C1141V18, CY7C1156V18, CY7C1143V18, and CY7C1145V18 follows.[2, 3, 4, 5, 6, 7]

Operation		K	RPS	WPS	DQ	DQ			DQ	DQ
Write Cycle:		L-H	H[8]	L[9]	D(A) at K(t + 1) ↑	D(A + 1) at			D(A + 2) at K(t + 2) ↑
							K(t + 1) ↑			D(A + 3) at K(t + 2) ↑
Load address on the rising
edge of K; input write data
on two consecutive K and
K rising edges
Read Cycle:		L-H	L[9]	X	Q(A) at K(t + 2) ↑	Q(A + 1) at			Q(A + 2) at K(t + 3)↑
								K(t + 2) ↑		Q(A + 3) at K(t + 3) ↑
(2.0 cycle Latency)
Load address on the rising
edge of K; wait one and a
half cycle; read data on
two consecutive K and	K
rising edges
NOP: No Operation		L-H	H	H	D = X	D = X			D = X	D = X
					Q = High-Z	Q = High-Z			Q = High-Z	Q = High-Z
Standby: Clock Stopped		Stopped	X	X	Previous State	Previous State			Previous State	Previous State

Notes

2.X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.

3.Device powers up deselected and the outputs in a tri-state condition.

4.“A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.

5.“t” represents the cycle at which a Read/Write operation is started. t + 1, t + 2, and t + 3 are the first, second, and third clock cycles respectively succeeding the “t” clock cycle.

6.Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.

7.IDo K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.

8.If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.

9.This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the second read orwrite request.

Document Number: 001-06583 Rev. *D Page 10 of 28

[+] Feedback