Contents
Main
CY7C1141V18, CY7C1156V18 CY7C1143V18, CY7C1145V18
18-Mbit QDR-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
Features
Configurations
Functional Description
Selection Guide
Logic Block Diagram (CY7C1141V18)
Logic Block Diagram (CY7C1156V18)
CY7C1143V18, CY7C1145V18
Document Number: 001-06583 Rev. *D Page 3 of 28
Logic Block Diagram (CY7C1143V18)
Logic Block Diagram (CY7C1145V18)
CY7C1141V18, CY7C1156V18 CY7C1143V18, CY7C1145V18
Pin Configurations
CY7C1141V18 (2M x 8)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1156V18 (2M x 9)
CY7C1141V18, CY7C1156V18 CY7C1143V18, CY7C1145V18
Pin Configurations
CY7C1143V18 (1M x 18)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1145V18 (512K x 36)
CY7C1141V18, CY7C1156V18
Pin Definitions
CY7C1141V18, CY7C1156V18 CY7C1143V18, CY7C1145V18
NC NC
Pin Definitions
CY7C1141V18, CY7C1156V18 CY7C1143V18, CY7C1145V18
Functional Overview
Read Operations
Write Operations
Byte Write Operations
Depth Expansion
Programmable Impedance
Echo Clocks
Valid Data Indicator (QVLD)
DLL
Application Example
Truth Table
SRAM #1
SRAM #4
BUS MASTER (CPU or ASIC)
CY7C1141V18, CY7C1156V18 CY7C1143V18, CY7C1145V18
Write Cycle Descriptions
Page
IEEE 1149.1 Serial Boundary Scan (JTAG)
Disabling the JTAG Feature
Test Access PortTest Clock
Test Mode Select
Test Data-In (TDI)
Page
CY7C1141V18, CY7C1156V18
TAP Controller State Diagram
TAP Controller Block Diagram
TAP Electrical Characteristics
TAP AC Switching Characteristics
TAP Timing and Test Condition
CY7C1141V18, CY7C1156V18 CY7C1143V18, CY7C1145V18
Identification Register Definitions
Scan Register Sizes
Instruction Codes
Boundary Scan Order
Power Up Sequence in QDR-II+ SRAM
Power Up Sequence
DLL Constraints
Power Up Waveforms
K K
Maximum Ratings
Operating Range
Electrical Characteristics
AC Electrical Characteristics
Capacitance
Thermal Resistance
AC Test Loads and Waveforms
ZQ ZQ
Switching Characteristics
Document Number: 001-06583 Rev. *D Page 24 of 28
Switching Waveforms Read/Write/Deselect Sequence
[+] Feedback [+] Feedback
t
Figure 7. Waveform for 2.0 Cycle Read Latency
QVLD
Page
Ordering Information
Document Number: 001-06583 Rev. *D Page 27 of 28
Package Diagram
[+] Feedback [+] Feedback
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
1.40 MAX.
Figure 8. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180
Document History Page