CY7C1302DV25
Document #: 38-05625 Rev. *A Page 14 of 18
Thermal Resistance[20]
Parameter Description Test Conditions 165 FBGA Package Unit
ΘJA Thermal Resistance (Junction to Ambient) Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
16.7 °C/W
ΘJC Thermal Resistance (Junction to Case) 2.5 °C/W
Capacitance[20]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 2.5V.
VDDQ = 1.5V
5pF
CCLK Clock Input Capacitance 6 pF
COOutput Capacitance 7 pF
AC Test Loads and Waveforms
Switching Characteristics Over the Operating Range [21]
Cypress
Parameter Consortium
Parameter Description
167 MHz
UnitMin. Max.
tPower[22] VCC (typical) to the First Access Read or Write 10 µs
Cycle Time
tCYC tKHKH K Clock and C Clock Cycle Time 6.0 ns
tKH tKHKL Input Clock (K/K and C/C) HIGH 2.4 ns
tKL tKLKH Input Clock (K/K and C/C) LOW 2.4 ns
tKHKHtKHKHK/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising edge
to rising edge) 2.7 3.3 ns
tKHCH tKHCH K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) 0.0 2.0 ns
Set-up Times
tSA tSA Address Set-up to Clock (K and K) Rise 0.7 ns
tSC tSC Control Set-up to Clock (K and K) Rise (RPS, WPS, BWS0, BWS1)0.7 ns
tSD tSD D[17:0] Set-up to Clock (K and K) Rise 0.7 ns
Hold Times
tHA tHA Address Hold after Clock (K and K) Rise 0.7 ns
tHC tHC Control Signals Hold after Clock (K and K) Rise
(RPS, WPS, BWS0, BWS1)0.7 ns
tHD tHD D[17:0] Hold after Clock (K and K) Rise 0.7 ns
Notes:
20.Tested initially and after any design or process change that may affect these parameters.
21.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250W, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC test loads.
22.This part has a voltage regulator that steps down the voltage internally; tPower is the time power needs to be supplied above VDD minimum initially before a read
or write operation can be initiated.
1.25V
0.25V
R = 50Ω
5pF
ALL INPUT PULSES
Device RL= 50Ω
Z0= 50Ω
VREF = 0.75V
VREF = 0.75V
[21]
0.75V
Under
Test
0.75V
Device
Under
Test
OUTPUT
0.75V
VREF
VREF
OUTPUT
ZQ
ZQ
(a)
Slew Rate = 2 V/ns
RQ =
250
Ω
(b)
RQ =
250
Ω
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