Cypress CY7C1302DV25 manual Features, Configurations, Functional Description

CY7C1302DV25

9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture

Features

•Separate independent Read and Write data ports

—Supports concurrent transactions

•167-MHz clock for high bandwidth

—2.5 ns Clock-to-Valid access time

•2-word burst on all accesses

•Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 333 MHz) @ 167 MHz

•Two input clocks (K and K) for precise DDR timing

—SRAM uses rising edges only

•Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.

•Single multiplexed address input bus latches address inputs for both Read and Write ports

•Separate Port Selects for depth expansion

•Synchronous internally self-timed writes

•2.5V core power supply with HSTL Inputs and Outputs

•Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

•Variable drive HSTL output buffers

•Expanded HSTL output voltage (1.4V–1.9V)

•JTAG Interface

Configurations

CY7C1302DV25 – 512K x 18

Functional Description

The CY7C1302DV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR™ architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data inputs to support Write operations. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of K clock. QDR has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Accesses to the CY7C1302DV25 Read and Write ports are completely independent of one another. All accesses are initiated synchronously on the rising edge of the positive input clock

(K). In order to maximize data throughput, both Read and Write ports are equipped with DDR interfaces. Therefore, data can be transferred into the device on every rising edge of both input clocks (K and K) and out of the device on every rising edge of the output clock (C and C, or K and K in a single clock domain) thereby maximizing performance while simplifying system design. Each address location is associated with two 18-bit words that burst sequentially into or out of the device.

Depth expansion is accomplished with a Port Select input for each port. Each Port Select allows each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Logic Block Diagram (CY7C1302DV25)
D[17:0]	18
			Write	Write
	Address		Data Reg	Data Reg
A(17:0)
	Register	Decode			Decode	Address		A(17:0)
18			256Kx18	256Kx18
						Register	18
		Add.	Memory	Memory	Add.
K	CLK		Array	Array
		Write			Read	Control	RPS
K	Gen.
						Logic	C
			Read Data Reg.
							C

Vref		36	18
							18
	Control			Reg.		Reg.		18
WPS		18
BWS0	Logic			Reg.
									Q[17:0]
BWS
					18
1

Cypress Semiconductor Corporation	•	198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-05625 Rev. *A		Revised March 23, 2006

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