Cypress CY7C1302DV25

CY7C1302DV25

Document #: 38-05625 Rev. *A Page 8 of 18

TAP Controller State Diagram[9]

Note:

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

TEST-LOGIC

RESET

TEST-LOGIC/

IDLE SELECT

DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDATE-DR

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

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Contents

Main 9-Mbit Burst of Two Pipelined SRAMs with Q DR Architecture CY7C1302DV25 Features CY7C1302DV25 Selection Guide Pin Configuration 165-ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1302DV25 (512K x 18) Pin Definitions CY7C1302DV25 Introduction Pin Definitions Application Example CY7C1302DV25 Truth Table Write Cycle Descriptions IEEE 1149.1 Serial Boundary Scan (JTAG) CY7C1302DV25 Page Page TAP Timing and Test Conditions Identification Register Definitions TAP AC Switching Characteristics Test Clock Test Mode Select TCK TMS Test Data-In TDI Test Data-Out TDO Scan Register Sizes Instruction Codes Boundary Scan Order CY7C1302DV25 Maximum Ratings Operating Range Electrical Characteristics Thermal Resistance Capacitance AC Test Loads and Waveforms Switching Characteristics Document #: 38-05625 Rev. *A Page 16 of 18 Switching Waveforms READ READ WRITE WRITEWRITE NOPREAD WRITE NOP 0 12345 8 1 67 Ordering Information 51-85180-*A SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40 MAX. 51-85180-*A Document History Page