CY7C1302DV25
Document #: 38-05625 Rev. *A Page 2 of 18

Selection Guide

CY7C1302DV25-167 Unit
Maximum Operating Frequency 167 MHz
Maximum Operating Current 500 mA

Pin Configuration

165-ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1302DV25 (512K x 18)

1 2 34567891011
ANC Gnd/144M NC/36M WPS BWS1KNC RPS NC/18M Gnd/72M NC
BNC Q9 D9 A NC K BWS0ANCNCQ8
CNC NC D10 VSS A A A VSS NC Q7 D8
DNC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
ENC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6
FNC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5
GNC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5
HNC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JNC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4
KNC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3
LNC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2
MNC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
NNC D17 Q16 VSS A A A VSS NC NC D1
PNC NC Q17 A A C A A NC D0 Q0
RTDOTCKAAACAAATMSTDI

Pin Definitions

Name I/O Description
D[17:0] Input-
Synchronous Data input signals, sampled on the rising edge of K and K clocks during valid Write opera-
tions.
WPS Input-
Synchronous Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active,
a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port
will cause D[17:0] to be ignored.
BWS0,
BWS1
Input-
Synchronous Byte Write Select 0, 1, active LOW. Sampled on the rising edge of the K and K clocks during
Write operations. Used to select which byte is written into the device during the current portion of
the Write operations. Bytes not written remain unaltered.
BWS0 controls D[8:0] and BWS1 controls D[17:9].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A Input-
Synchronous Address Inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks
for active Read and Write operations. These address inputs are multiplexed for both Read and
Write operations. Internally, the device is organized as 512K x 18 (2 arrays each of 256K x 18).
These inputs are ignored when the appropriate port is deselected.
Q[17:0] Outputs-
Synchronous Data Output signals. These pins drive out the requested data during a Read operation. Valid data
is driven out on the rising edge of both the C and C clocks during Read operations or K and K
when in single clock mode. When the Read port is deselected, Q[17:0] are automatically
three-stated.
RPS Input-
Synchronous Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When
active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
three-stated following the next rising edge of the C clock. Each read access consists of a burst of
two sequential transfers.
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