Cypress CY7C1302DV25 Switching Waveforms

CY7C1302DV25

Document #: 38-05625 Rev. *A Page 16 of 18

Switching Waveforms[25, 26, 27]

Notes:

25.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0 i.e., A0+1.

26.Outputs are disabled (High-Z) one clock cycle after a NOP.

27.In this example, if address A2=A1 then data Q20=D10 and Q21=D11. Write data is forwarded immediately as read results.This note applies to the whole diagram.

READ READ WRITE WRITEWRITE NOPREAD WRITE NOP

12345 8 1

0

67

RPS

D10

tKH tKHKH

tKHCH tCO

tKL tCYC

tHC

tSA tHA

tHD

tKHCH

DON’T CARE UNDEFINE

tCLZ tCHZ

tSC

tKH tKL

A2 A3 A4 A5 A6

tHA

D11 D30 D31 D50 D51 D60 D61

tSD tHD

Q00 Q21Q01 Q20 Q40 Q41

tCO

tDOH tDOH

tKHKH tCYC

9

tSA

tSD

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Contents

Main 9-Mbit Burst of Two Pipelined SRAMs with Q DR Architecture CY7C1302DV25 Features CY7C1302DV25 Selection Guide Pin Configuration 165-ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1302DV25 (512K x 18) Pin Definitions CY7C1302DV25 Introduction Pin Definitions Application Example CY7C1302DV25 Truth Table Write Cycle Descriptions IEEE 1149.1 Serial Boundary Scan (JTAG) CY7C1302DV25 Page Page TAP Timing and Test Conditions Identification Register Definitions TAP AC Switching Characteristics Test Clock Test Mode Select TCK TMS Test Data-In TDI Test Data-Out TDO Scan Register Sizes Instruction Codes Boundary Scan Order CY7C1302DV25 Maximum Ratings Operating Range Electrical Characteristics Thermal Resistance Capacitance AC Test Loads and Waveforms Switching Characteristics Document #: 38-05625 Rev. *A Page 16 of 18 Switching Waveforms READ READ WRITE WRITEWRITE NOPREAD WRITE NOP 0 12345 8 1 67 Ordering Information 51-85180-*A SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40 MAX. 51-85180-*A Document History Page