Cypress CY7C1302DV25 Switching Characteristics

CY7C1302DV25

Document #: 38-05625 Rev. *A Page 15 of 18

Output Times

tCO tCHQV C/C Clock Rise (or K/K in single clock mode) to Data Valid 2.5 ns

tDOH tCHQX Data Output Hold after Output C/C Clock Rise (Active to Active) 1.2 ns

tCHZ tCHZ Clock (C and C) Rise to High-Z (Active to High-Z)[23, 24] 2.5 ns

tCLZ tCLZ Clock (C and C) Rise to Low-Z[23, 24] 1.2 ns

Notes:

23.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

24.At any given voltage and temperature tCHZ is less than tCLZ and, tCHZ less than tCO.

Switching Characteristics Over the Operating Range (continued)[21]

Cypress

Parameter Consortium

Parameter Description

167 MHz

UnitMin. Max.

[+] Feedback

Contents

Main 9-Mbit Burst of Two Pipelined SRAMs with Q DR Architecture CY7C1302DV25 Features CY7C1302DV25 Selection Guide Pin Configuration 165-ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1302DV25 (512K x 18) Pin Definitions CY7C1302DV25 Introduction Pin Definitions Application Example CY7C1302DV25 Truth Table Write Cycle Descriptions IEEE 1149.1 Serial Boundary Scan (JTAG) CY7C1302DV25 Page Page TAP Timing and Test Conditions Identification Register Definitions TAP AC Switching Characteristics Test Clock Test Mode Select TCK TMS Test Data-In TDI Test Data-Out TDO Scan Register Sizes Instruction Codes Boundary Scan Order CY7C1302DV25 Maximum Ratings Operating Range Electrical Characteristics Thermal Resistance Capacitance AC Test Loads and Waveforms Switching Characteristics Document #: 38-05625 Rev. *A Page 16 of 18 Switching Waveforms READ READ WRITE WRITEWRITE NOPREAD WRITE NOP 0 12345 8 1 67 Ordering Information 51-85180-*A SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40 MAX. 51-85180-*A Document History Page