Cypress Logic Block Diagram CY7C1303BV25, Logic Block Diagram CY7C1306BV25, Selection Guide

							CY7C1303BV25
							CY7C1306BV25
Logic Block Diagram (CY7C1303BV25)
D[17:0]	18
			Write	Write
	Address		Data Reg	Data Reg
A(18:0)
	Register	Decode			Decode	Address		A(18:0)
19			512Kx18	512Kx18			19
						Register
		Add.	Memory	Memory	Add.
K	CLK		Array	Array
K		Write			Read	Control	RPS
	Gen.
						Logic	C
			Read Data Reg.
							C

Vref			36	18
								18
		Control			Reg.		Reg.		18
WPS			18
BWS0		Logic			Reg.
										Q[17:0]
BWS	1					18

Logic Block Diagram (CY7C1306BV25)

D[35:0]	36
			Write	Write
	Address		Data Reg	Data Reg
A(17:0)
	Register	Decode			Decode	Address		A(17:0)
18			256Kx36	256Kx36			18
						Register
		Add.	Memory	Memory	Add.
K	CLK		Array	Array
K		Write			Read	Control	RPS
	Gen.
						Logic	C
			Read Data Reg.
							C

	Vref					72	36
											36
					Control			Reg.		Reg.		36
	WPS					36
BWS0					Logic
								Reg.
													Q[35:0]
	BWS			1					36
BWS		2
BWS			3

Selection Guide

		CY7C1303BV25-167	Unit
		CY7C1306BV25-167
	Maximum Operating Frequency	167	MHz
	Maximum Operating Current	500	mA
Document #: 38-05627 Rev. *A			Page 2 of 19

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