Cypress CY7C1314AV18, CY7C1312AV18 manual Features, Configurations, Functional Description

CY7C1310AV18

CY7C1312AV18

PRELIMINARYCY7C1314AV18

18-Mb QDR™-II SRAM 2-Word Burst Architecture

Features

•Separate independent Read and Write data ports

—Supports concurrent transactions

•167-MHz clock for high bandwidth

•2-Word Burst on all accesses

•Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 333 MHz) @ 167MHz

•Two input clocks (K and K) for precise DDR timing

—SRAM uses rising edges only

•Two output clocks (C and C) account for clock skew and flight time mismatching

•Echo clocks (CQ and CQ) simplify data capture in high speed systems

•Single multiplexed address input bus latches address inputs for both Read and Write ports

•Separate Port Selects for depth expansion

•Synchronous internally self-timed writes

•Available in x8, x18, and x36 configurations

•Full data coherancy , providing most current data

•Core Vdd=1.8V(+/-0.1V);I/O Vddq=1.4V to Vdd

•13 x 15 x 1.4 mm 1.0-mm pitch FBGA package, 165 ball (11x15 matrix)

•Variable drive HSTL output buffers

•JTAG 1149.1 compatible test access port

•Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1310AV18 – 2M x 8

CY7C1312AV18 – 1M x 18

CY7C1314AV18 – 512K x 36

Functional Description

The CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write opera- tions. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with two 8-bit words (CY7C1310AV18) or 18-bit words (CY7C1312AV18) or 36-bit words (CY7C1314AV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds.”

Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Logic Block Diagram (CY7C1310AV18)

D[7:0] 8

A(19:0) 20

K

K

DOFF

Address

Register

CLK

Gen.

	Write	Write
				Address
	Reg	Reg
				Register
Decode	1M x 8	1M x 8	Decode
Write Add.	Array	Array	Read Add.		Control
					Logic
	Read Data Reg.
		16

20A(19:0)

RPS

C

C		CQ
	CQ

VREF
WPS		Control
BWS		Logic
	[1:0]

	8				8
		Reg.		Reg.
8
		Reg.
			8

8

Q[7:0]

Cypress Semiconductor Corporation	•	3901 North First Street	•	San Jose, CA 95134	•	408-943-2600
Document #: 38-05497 Rev. *A				Revised June 1, 2004

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