Logic Block Diagram CY7C1312AV18 | Cypress CY7C1310AV18 specification

CY7C1310AV18

CY7C1312AV18

PRELIMINARYCY7C1314AV18

Logic Block Diagram (CY7C1312AV18)

D[17:0]

Write

Address

Reg

Address

512Kx

A(18:0) 19

Decode

512Kx

Decode

Add.Write

18Array

Add.Read

Logic

Gen.

CLK

Control

DOFF

Read Data Reg.

VREF

Reg.

WPS

Control

Logic

BWS[1:0]

Reg.

19A(18:0)

RPS

CCQ CQ

Q[17:0]

Logic Block Diagram (CY7C1314AV18)

D[35:0]

Write

Address

Reg

Address

256Kx

A(17:0) 18

Decode

256Kx

Decode

Add.Write

36Array

Add.Read

Logic

Gen.

CLK

Control

DOFF

Read Data Reg.

VREF

Reg.

WPS

Control

Logic

BWS[3:0]

Reg.

18A(17:0)

RPS

CCQ CQ

36 Q[35:0]

Selection Guide

	167 MHz	133 MHz	Unit
Maximum Operating Frequency	167	133	MHz

Maximum Operating Current	800	700	mA

Document #: 38-05497 Rev. *A

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Cypress CY7C1310AV18 Logic Block Diagram CY7C1312AV18, Logic Block Diagram CY7C1314AV18, Selection Guide, MHz 133 MHz Unit

Contents

Logic Block Diagram CY7C1310AV18 FeaturesConfigurations Functional Description Selection Guide Logic Block Diagram CY7C1312AV18Logic Block Diagram CY7C1314AV18 167 MHz 133 MHz Unit TMS TDI Pin ConfigurationsVSS Operations Pin DefinitionsPin Name Pin Description WPS Is referenced with respect to Negative Output Clock InputNegative Input Clock Input TDO for Jtag Introduction RPS WPS Application Example1DLL Comments Write Cycle Descriptions CY7C1314AV18 2BWS Maximum Ratings DC Electrical Characteristics Over the Operating Range9,14AC Electrical Characteristics Over the Operating Range Operating Range Switching Characteristics Over the Operating Range 16,17 Thermal Resistance20 Parameter Description Test Conditions Max Unit Capacitance20AC Test Loads and Waveforms Input Capacitance TA = 25C, f = 1 MHz VDD = Preliminary Read/Write/Deselect Sequence Ieee 1149.1 Serial Boundary Scan Jtag Idcode Bypass Sample ZSAMPLE/PRELOAD Extest TAP Controller State Diagram24 EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller Block Diagram Parameter Description Test Conditions Min Max Unit Parameter Description Min Max Unit TAP AC Switching Characteristics Over the Operating Range26TAP Timing and Test Conditions27 Instruction Codes Identification Register DefinitionsScan Register Sizes Boundary Scan Order 10F Package Diagram Ordering Information DIM Document HistoryREV VBL

Cypress CY7C1310AV18 manual Logic Block Diagram CY7C1312AV18, Logic Block Diagram CY7C1314AV18

Models: CY7C1310AV18 CY7C1312AV18 CY7C1314AV18

Logic Block Diagram (CY7C1312AV18)

DOFF

Logic Block Diagram (CY7C1314AV18)

DOFF

Selection Guide

167 MHz

133 MHz

Unit