Cypress CY7C1310AV18, CY7C1312AV18, CY7C1314AV18 CY7C1312AV18, PRELIMINARY

CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
Document #: 38-05497 Rev. *A Page 2 of 21
Selection Guide
167 MHz 133 MHz Unit
Maximum Operating Frequency 167 133 MHz
Maximum Operating Current 800 700 mA
Logic Block Diagram (CY7C1312AV18)
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q
[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
19
18
36
18
BWS
[1:0]
V
REF
Write Add. Decode
18
A
(18:0)
19
C
C
18
512K x 18 Array
512K x 18 Array
Write
Reg
Write
Reg
CQ
CQ
18
DOFF
Logic Block Diagram (CY7C1314AV18)
CLK
A
(17:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q
[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
18
36
72
36
BWS
[3:0]
V
REF
Write Add. Decode
36
A
(17:0)
18
C
C
36
256K x 36 Array
256K x 36 Array
Write
Reg
Write
Reg
CQ
CQ
36
DOFF
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