10F | Cypress CY7C1314AV18, CY7C1312AV18, CY7C1310AV18 guide

CY7C1310AV18

CY7C1312AV18

PRELIMINARYCY7C1314AV18

Document #: 38-05497 Rev. *A

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Contents

Functional Description FeaturesConfigurations Logic Block Diagram CY7C1310AV18 167 MHz 133 MHz Unit Logic Block Diagram CY7C1312AV18Logic Block Diagram CY7C1314AV18 Selection Guide VSS Pin ConfigurationsTMS TDI WPS Pin DefinitionsPin Name Pin Description Operations TDO for Jtag Negative Output Clock InputNegative Input Clock Input Is referenced with respect to Introduction DLL Application Example1RPS WPS BWS Write Cycle Descriptions CY7C1314AV18 2Comments Operating Range DC Electrical Characteristics Over the Operating Range9,14AC Electrical Characteristics Over the Operating Range Maximum Ratings Thermal Resistance20 Switching Characteristics Over the Operating Range 16,17 Input Capacitance TA = 25C, f = 1 MHz VDD = Capacitance20AC Test Loads and Waveforms Parameter Description Test Conditions Max Unit Read/Write/Deselect Sequence Preliminary Idcode Ieee 1149.1 Serial Boundary Scan Jtag Extest Sample ZSAMPLE/PRELOAD Bypass EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram24 Parameter Description Test Conditions Min Max Unit TAP Controller Block Diagram TAP Timing and Test Conditions27 TAP AC Switching Characteristics Over the Operating Range26Parameter Description Min Max Unit Boundary Scan Order Identification Register DefinitionsScan Register Sizes Instruction Codes 10F Ordering Information Package Diagram VBL Document HistoryREV DIM