Ordering Information, Package Diagram

	CY7C1310AV18
PRELIMINARY	CY7C1312AV18
PRELIMINARY	CY7C1314AV18

Ordering Information

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Name	Package Type	Range

167	CY7C1310AV18-167BZC	BB165D	13 x 15 x 1.4 mm FBGA	Commercial
	CY7C1312AV18-167BZC

	CY7C1314AV18-167BZC

133	CY7C1310AV18-133BZC	BB165D	13 x 15 x 1.4 mm FBGA	Commercial
	CY7C1312AV18-133BZC

	CY7C1314AV18-133BZC

Package Diagram

165 FBGA 13 x 15 x 1.40 mm BB165D

51-85180-**

QDR SRAMs and Quad Data Rate SRAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC and Samsung technology. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05497 Rev. *A

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Cypress CY7C1310AV18, CY7C1312AV18, CY7C1314AV18 manual Ordering Information, Package Diagram

Contents

Features ConfigurationsLogic Block Diagram CY7C1310AV18 Functional Description Logic Block Diagram CY7C1312AV18 Logic Block Diagram CY7C1314AV18Selection Guide 167 MHz 133 MHz Unit TMS TDI Pin ConfigurationsVSS Pin Definitions Pin Name Pin DescriptionOperations WPS Negative Output Clock Input Negative Input Clock InputIs referenced with respect to TDO for Jtag Introduction RPS WPS Application Example1DLL Comments Write Cycle Descriptions CY7C1314AV18 2BWS DC Electrical Characteristics Over the Operating Range9,14 AC Electrical Characteristics Over the Operating RangeMaximum Ratings Operating Range Switching Characteristics Over the Operating Range 16,17 Thermal Resistance20 Capacitance20 AC Test Loads and WaveformsParameter Description Test Conditions Max Unit Input Capacitance TA = 25C, f = 1 MHz VDD = Preliminary Read/Write/Deselect Sequence Ieee 1149.1 Serial Boundary Scan Jtag Idcode Sample Z SAMPLE/PRELOADBypass Extest TAP Controller State Diagram24 EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller Block Diagram Parameter Description Test Conditions Min Max Unit Parameter Description Min Max Unit TAP AC Switching Characteristics Over the Operating Range26TAP Timing and Test Conditions27 Identification Register Definitions Scan Register SizesInstruction Codes Boundary Scan Order 10F Package Diagram Ordering Information Document History REVDIM VBL

PRELIMINARY

CY7C1314AV18

Ordering Information

Package Diagram

165 FBGA 13 x 15 x 1.40 mm BB165D