Cypress CY7C1310AV18, CY7C1312AV18, CY7C1314AV18 Switching Waveforms

CY7C1310AV18

CY7C1312AV18

CY7C1314AV18

PRELIMINARY

Document #: 38-05497 Rev. *A Page 12 of 21

Switching Waveforms[21,22,23]

Notes:

21.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0 i.e., A0+1.

22.Output are disabled (High-Z) one clock cycle after a NOP.

23.In this example , if address A2=A1,then data Q20=D10 and Q21=D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.,

Read/Write/Deselect Sequence

12345 8 10

67

RPS

READ READ WRITE WRITEWRITE

tKH tKHKH

tKHCH

tCO

tKL tCYC

tSA tHA

tSD tHD

tKHCH

NOP

DON’T CARE UNDEFINED

tCLZ tCHZ

tKH

tKL

tSA tHA

D30 D50 D51 D61

tSD tHD

READ WRITE NOP

Q00 Q01 Q20

tCO

tDOH

tKHKH tCYC

9

A6A5

A3 A4A1 A2

Q21 Q40 Q41

D31D11D10 D60

tCQD

tDOH

tCCQO

tCQOH

tCCQO

tCQOH

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Contents

Main PRELIMINARY 18-Mb QDR-II SRAM 2-Word Burst Architecture L CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 Features Configurations CY7C1312AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 2 of 21 Selection Guide 167 MHz 133 MHz Unit Maximum Operating Frequency 167 133 MHz Maximum Operating Current 800 700 mA CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Pin Configurations CY7C1310AV18 (2M 8) 11 15 BGA CY7C1312AV18 (1M 18) 11 15 BGA CY7C1314AV18 PRELIMINARY Pin Definitions Pin Configurations CY7C1314AV18 (512k 36) 11 15 BGA Pin Definitions Introduction Pin Definitions CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Application Example Truth Table CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Write Cycle Descriptions Maximum Ratings Operating Range DC Electrical Characteristics AC Electrical Characteristics Switching Characteristics Thermal Resistance Document #: 38-05497 Rev. *A Page 11 of 21 Capacitance [+] Feedback 5pF CCLK Clock Input Capacitance 6 pF COOutput Capacitance 7 pF AC Test Loads and Waveforms ZQ ZQ Switching Waveforms [+] Feedback 12345 8 10 Read/Write/Deselect Sequence 67 CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY IEEE 1149.1 Serial Boundary Scan (JTAG) Page Page TAP Controller TAP AC Switching Characteristics TAP Timing and Test Conditions Test Clock Test Mode Select TCK TMS Test Data-In TDI Test Data-Out TDO CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Identification Register Definitions Scan Register Sizes Instruction Codes Page Ordering Information Package Diagram 165 FBGA 13 x 15 x 1.40 mm BB165D