Cypress CY7C1310AV18, CY7C1312AV18, CY7C1314AV18 TAP Controller

CY7C1310AV18

CY7C1312AV18

CY7C1314AV18

PRELIMINARY

Document #: 38-05497 Rev. *A Page 16 of 21

TAP Controller Block Diagram

TAP Electrical Characteristics Over the Operating Range[9,12,25]

Parameter Description Test Conditions Min. Max. Unit

VOH1 Output HIGH Voltage IOH = −2.0 mA 1.4 V

VOH2 Output HIGH Voltage IOH = −100 µA1.6V

VOL1 Output LOW Voltage IOL = 2.0 mA 0.4 V

VOL2 Output LOW Voltage IOL = 100 µA0.2V

VIH Input HIGH Voltage 0.65VDD VDD + 0.3 V

VIL Input LOW Voltage –0.3 0.35 VDD V

IXInput and OutputLoad Current GND ≤ VI ≤ VDD −55µA

Note:

25.These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.

012..

3031

Boundary Scan Register

Identification Register

012..

106

012

Instruction Register

Bypass Register

Selection

Circuitry Selection

Circuitry

TAP Controller

TDI TDO

TCK

TMS

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Contents

Main PRELIMINARY 18-Mb QDR-II SRAM 2-Word Burst Architecture L CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 Features Configurations CY7C1312AV18 PRELIMINARY Document #: 38-05497 Rev. *A Page 2 of 21 Selection Guide 167 MHz 133 MHz Unit Maximum Operating Frequency 167 133 MHz Maximum Operating Current 800 700 mA CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Pin Configurations CY7C1310AV18 (2M 8) 11 15 BGA CY7C1312AV18 (1M 18) 11 15 BGA CY7C1314AV18 PRELIMINARY Pin Definitions Pin Configurations CY7C1314AV18 (512k 36) 11 15 BGA Pin Definitions Introduction Pin Definitions CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Application Example Truth Table CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Write Cycle Descriptions Maximum Ratings Operating Range DC Electrical Characteristics AC Electrical Characteristics Switching Characteristics Thermal Resistance Document #: 38-05497 Rev. *A Page 11 of 21 Capacitance [+] Feedback 5pF CCLK Clock Input Capacitance 6 pF COOutput Capacitance 7 pF AC Test Loads and Waveforms ZQ ZQ Switching Waveforms [+] Feedback 12345 8 10 Read/Write/Deselect Sequence 67 CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY IEEE 1149.1 Serial Boundary Scan (JTAG) Page Page TAP Controller TAP AC Switching Characteristics TAP Timing and Test Conditions Test Clock Test Mode Select TCK TMS Test Data-In TDI Test Data-Out TDO CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY Identification Register Definitions Scan Register Sizes Instruction Codes Page Ordering Information Package Diagram 165 FBGA 13 x 15 x 1.40 mm BB165D