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Cypress CY7C1910BV18, CY7C1314BV18 TAP Controller Block Diagram, TAP Electrical Characteristics

Models: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 CY7C1310BV18

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CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18

TAP Controller Block Diagram


																						0
																						0

																			Bypass Register

TDI						Selection													2	1		0						Selection
																			2	1		0

														Instruction Register
						Circuitry								Instruction Register
																												Circuitry
												31		30	29	.	.		2	1		0						Circuitry



														Identification Register

												106		.	.	.	.		2	1		0



														Boundary Scan Register

	TCK

																TAP Controller

	TMS
	TMS

TDO

TAP Electrical Characteristics

Over the Operating Range [10, 11, 12]

Parameter	Description	Test Conditions	Min	Max	Unit
VOH1	Output HIGH Voltage	IOH = −2.0 mA	1.4		V
VOH2	Output HIGH Voltage	IOH = −100 μA	1.6		V
VOL1	Output LOW Voltage	IOL = 2.0 mA		0.4	V
VOL2	Output LOW Voltage	IOL = 100 μA		0.2	V
VIH	Input HIGH Voltage		0.65VDD	VDD + 0.3	V
VIL	Input LOW Voltage		–0.3	0.35VDD	V
IX	Input and Output Load Current	GND ≤ VI ≤ VDD	–5	5	μA

Notes

10.These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.

11.Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −1.5V (Pulse width less than tCYC/2).

12.All Voltage referenced to Ground.

Document #: 38-05619 Rev. *F

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Cypress CY7C1910BV18, CY7C1314BV18, CY7C1310BV18, CY7C1312BV18 TAP Controller Block Diagram, TAP Electrical Characteristics

Contents

Selection Guide FeaturesConfigurations Functional Description Logic Block Diagram CY7C1310BV18 Logic Block Diagram CY7C1910BV18Doff Logic Block Diagram CY7C1314BV18 Logic Block Diagram CY7C1312BV18 CY7C1910BV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1310BV18 2M x NC/72M NC/36M CY7C1312BV18 1M xWPS BWS CY7C1314BV18 512K x Pin Name Pin Description Pin Definitions TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Referenced with Respect to Functional Overview Sram #1 Application ExampleProgrammable Impedance Echo Clocks Comments Truth TableWrite Cycle Descriptions Operation Into the device. D359 remains unaltered Write cycle description table for CY7C1910BV18 followsWrite cycle description table for CY7C1314BV18 follows Device Ieee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block Diagram TAP Timing and Test Conditions TAP AC Switching Characteristics Register Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction Codes Bit # Bump ID Boundary Scan Order Power Up Sequence in QDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Input High Voltage Vref +Input LOW Voltage Vref Document # 38-05619 Rev. *F Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max Unit DLL Timing Switching CharacteristicsCypress Consortium Description 250 MHz 200 MHz 167 MHz Unit Parameter Min Max Read/Write/Deselect Sequence 26, 27 Switching Waveforms Ordering Information 167 Ball Fbga 13 x 15 x 1.4 mm Package Diagram Document History SYTNXR VKN/PYRS Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions VKN