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Cypress CY7C1310BV18, CY7C1312BV18, CY7C1314BV18, CY7C1910BV18 Switching Waveforms

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CY7C1310BV18, CY7C1910BV18

CY7C1312BV18, CY7C1314BV18

Document #: 38-05619 Rev. *F Page 24 of 29

Switching Waveforms

Figure 5. Read/Write/Deselect Sequence [26, 27, 28]

1234 5810

67

RPS

WPS

READ READ WRITE WRITEWRITE NOPREAD WRITE NOP

9

tKH tKHKH

tKL tCYC

tSA tHA

tSD tHD

SC t

tSA tHA

tSD tHD

A6A5

A3 A4

A1 A2

D30 D50 D51 D61

D31

D11D10 D60

DON’T CARE UNDEFINED

tKHCH

tCO

tKHCH

tCLZ CHZ

tKH

tKL

Q00 Q01 Q20

tKHKH tCYC

Q21 Q40 Q41

tCQD

tDOH

tCCQO

tCQOH

tCCQO

tCQOH

tCQDOH

Notes

26.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.

27.Outputs are disabled (High-Z) one clock cycle after a NOP.

28.In this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.

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Contents

Main 18-Mbit QDR-II SRAM 2-Word Burst Architecture CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Features Configurations Functional Description CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 2 of 29 Logic Block Diagram (CY7C1310BV18) Logic Block Diagram (CY7C1910BV18) CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev. *F Page 3 of 29 Logic Block Diagram (CY7C1312BV18) Logic Block Diagram (CY7C1314BV18) CY7C1312BV18, CY7C1314BV18 Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout Pin Definitions CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Pin Definitions CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Functional Overview Read Operations Write Operations Byte Write Operations CY7C1310BV18, CY7C1910BV18 Programmable Impedance Echo Clocks DLL Application Example CY7C1310BV18, CY7C1910BV18 Truth Table Write Cycle Descriptions Page CY7C1312BV18, CY7C1314BV18 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 CY7C1312BV18, CY7C1314BV18 TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Boundary Scan Order CY7C1310BV18, CY7C1910BV18 Power Up Sequence in QDR-II SRAM VV Power Up Sequence DLL Constraints Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics AC Electrical Characteristics Electrical Characteristics DC Electrical Characteristics Capacitance Thermal Resistance Switching Characteristics Document #: 38-05619 Rev. *F Page 24 of 29 Switching Waveforms Figure 5. Read/Write/Deselect Sequence 1234 5810 67 READ READ WRITE WRITEWRITE NOPREAD WRITE NOP 9 Page Ordering Information Document #: 38-05619 Rev. *F Page 27 of 29 Package Diagram [+] Feedback SOLDERPAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40MAX. Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions Document History Page