Cypress CY7C1310BV18, CY7C1312BV18, CY7C1314BV18, CY7C1910BV18 Switching Characteristics

CY7C1310BV18, CY7C1910BV18
CY7C1312BV18, CY7C1314BV18
Document #: 38-05619 Rev. *F Page 23 of 29
Switching Characteristics
Over the Operating Range [20, 21]
Cypress
Parameter Consortium Parameter Description 250 MHz 200 MHz 167 MHz Unit
Min Max Min Max Min Max
tPOWER VDD(Typical) to the First Access [22] 111ms
tCYC tKHKH K Clock and C Clock Cycle Time 4.0 8.4 5.0 8.4 6.0 8.4 ns
tKH tKHKL Input Clock (K/K and C/C) HIGH 1.6–2.0–2.4– ns
tKL tKLKH Input Clock (K/K and C/C) LOW 1.6 – 2.0 – 2.4 – ns
tKHKHtKHKHK Clock Rise to K Clock Rise and C to C Rise
(rising edge to rising edge) 1.8–2.2–2.7– ns
tKHCH tKHCH K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) 0 1.8 0 2.2 0 2.7 ns
Setup Times
tSA tAVKH Address Setup to K Clock Rise 0.35–0.4–0.5– ns
tSC tIVKH Control Setup to K Clock Rise (RPS, WPS) 0.35–0.4–0.5– ns
tSCDDR tIVKH DDR Control Setup to Clock (K/K) Rise
(BWS0, BWS1, BWS3, BWS4)0.35 – 0.4 – 0.5 – ns
tSD [23] tDVKH D[X:0] Setup to Clock (K/K) Rise 0.35–0.4–0.5– ns
Hold Times
tHA tKHAX Address Hold after K Clock Rise 0.35 – 0.4 – 0.5 – ns
tHC tKHIX Control Hold after K Clock Rise (RPS, WPS) 0.35–0.4–0.5– ns
tHCDDR tKHIX DDR Control Hold after Clock (K/K) Rise
(BWS0, BWS1, BWS3, BWS4)0.35 – 0.4 – 0.5 – ns
tHD tKHDX D[X:0] Hold after Clock (K/K) Rise 0.35 – 0.4 – 0.5 – ns
Output Times
tCO tCHQV C/C Clock Rise (or K/K in Single Clock Mode) to Data Valid – 0.45 – 0.45 – 0.50 ns
tDOH tCHQX Data Output Hold after Output C/C Clock Rise
(Active to Active) –0.45 – –0.45 – –0.50 – ns
tCCQO tCHCQV C/C Clock Rise to Echo Clock Valid – 0.45 – 0.45 – 0.50 ns
tCQOH tCHCQX Echo Clock Hold after C/C Clock Rise –0.45 – –0.45 – –0.50 – ns
tCQD tCQHQV Echo Clock High to Data Valid – 0.30 – 0.35 – 0.40 ns
tCQDOH tCQHQX Echo Clock High to Data Invalid –0.30 – –0.35 – –0.40 – ns
tCHZ tCHQZ Clock (C/C) Rise to High-Z (Active to High-Z) [24, 25] –0.45–0.45–0.50ns
tCLZ tCHQX1 Clock (C/C) Rise to Low-Z [24, 25] –0.45 – –0.45 – –0.50 – ns
DLL Timing
tKC Var tKC Var Clock Phase Jitter – 0.20 – 0.20 – 0.20 ns
tKC lock tKC lock DLL Lock Time (K, C) 1024 – 1024 – 1024 – Cycles
tKC Reset tKC Reset K Static to DLL Reset 30 – 30 – 30 – ns
Notes
21.When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timing of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
22.This part has a voltage regulator internally; tPOWER is the time that the power is supplied above VDD minimum initially before a read or write operation is initiated.
23.For D2 data signal on CY7C1910BV18 device, tSD is 0.5 ns for 200 MHz, and 250 MHz frequencies.
24.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±100 mV from steady state voltage.
25.At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
[+] Feedback