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Cypress CY7C1310BV18, CY7C1314BV18 manual AC Electrical Characteristics, Input High Voltage Vref +

Models: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 CY7C1310BV18

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CY7C1310BV18, CY7C1910BV18

CY7C1312BV18, CY7C1314BV18

Electrical Characteristics (continued)

DC Electrical Characteristics

Over the Operating Range [12]

Parameter	Description	Test Conditions			Min	Typ	Max	Unit
ISB1	Automatic Power Down	Max VDD,	250 MHz	(x8)			400	mA
	Current	Both Ports Deselected,
	Current	Both Ports Deselected,		(x9)			400
		VIN ≥ VIH or VIN ≤ VIL		(x9)			400

				(x18)			400
		f = fMAX = 1/tCYC,		(x18)			400
		Inputs Static		(x36)			450

			200 MHz	(x8)			380	mA

				(x9)			380

				(x18)			380

				(x36)			400

			167 MHz	(x8)			360	mA

				(x9)			360

				(x18)			360

				(x36)			370

AC Electrical Characteristics

Over the Operating Range [11]

Parameter	Description	Test Conditions	Min	Typ	Max	Unit
VIH	Input HIGH Voltage		VREF + 0.2	–	–	V
VIL	Input LOW Voltage		–	–	VREF – 0.2	V

Document #: 38-05619 Rev. *F

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Cypress CY7C1310BV18, CY7C1314BV18, CY7C1312BV18, CY7C1910BV18 manual AC Electrical Characteristics, Input High Voltage Vref +

Contents

Configurations FeaturesFunctional Description Selection Guide Logic Block Diagram CY7C1310BV18 Logic Block Diagram CY7C1910BV18Doff Logic Block Diagram CY7C1314BV18 Logic Block Diagram CY7C1312BV18 Ball Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1310BV18 2M x CY7C1910BV18 2M x WPS BWS CY7C1312BV18 1M xCY7C1314BV18 512K x NC/72M NC/36M Pin Name Pin Description Pin Definitions Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for Jtag Functional Overview Programmable Impedance Application ExampleEcho Clocks Sram #1 Write Cycle Descriptions Truth TableOperation Comments Write cycle description table for CY7C1314BV18 follows Write cycle description table for CY7C1910BV18 followsDevice Into the device. D359 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block Diagram TAP Timing and Test Conditions TAP AC Switching Characteristics Scan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit Size Bit # Bump ID Boundary Scan Order Power Up Sequence in QDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Input High Voltage Vref +Input LOW Voltage Vref Document # 38-05619 Rev. *F Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga Unit Cypress Consortium Description 250 MHz 200 MHz 167 MHz Unit Switching CharacteristicsParameter Min Max DLL Timing Read/Write/Deselect Sequence 26, 27 Switching Waveforms Ordering Information 167 Ball Fbga 13 x 15 x 1.4 mm Package Diagram Document History SYTNXR Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationVKN VKN/PYRS