Cypress CY7C1310BV18, CY7C1312BV18, CY7C1314BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18

CY7C1310BV18, CY7C1910BV18
CY7C1312BV18, CY7C1314BV18
Document #: 38-05619 Rev. *F Page 2 of 29
Logic Block Diagram (CY7C1310BV18)
Logic Block Diagram (CY7C1910BV18)
1M x 8 Array
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
8
20
16
8
NWS[1:0]
VREF
Write Add. Decode
Write
Reg
8
A(19:0)
20
CQ
CQ
DOFF
Q[7:0]
8
8
8
Write
Reg
C
C
1M x 8 Array
1M x 9 Array
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
9
20
18
9
BWS[0]
VREF
Write Add. Decode
Write
Reg
9
A(19:0)
20
CQ
CQ
DOFF
Q[8:0]
9
9
9
Write
Reg
C
C
1M x 9 Array
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