Cypress CY7C1312BV18 Logic Block Diagram CY7C1310BV18, Logic Block Diagram CY7C1910BV18, Doff

CY7C1310BV18, CY7C1910BV18

CY7C1312BV18, CY7C1314BV18

Logic Block Diagram (CY7C1310BV18)

8

D[7:0]

20Address

A(19:0) Register

K

K CLK

Gen.

DOFF

VREF		Control
WPS
		Logic
NWS
	[1:0]

Write Add. Decode

Write		Write
Reg		Reg
1M x		1M x	Decode
8 Array		8 Array	Read Add.
Read Data Reg.
	16	8
				Reg.
		8
				Reg.

Address

Register

Control

Logic

Reg.

20A(19:0)

	RPS
	C
	C
			CQ
8		CQ
	8
8		Q[7:0]

Logic Block Diagram (CY7C1910BV18)

9

D[8:0]

20Address

A(19:0) Register

K

K CLK

Gen.

DOFF

VREF		Control
WPS
		Logic
BWS
	[0]

Write Add. Decode

Write		Write
Reg		Reg
1M x		1M x	Decode
9 Array		9 Array	Read Add.
Read Data Reg.
	18	9
				Reg.
		9
				Reg.

Address

Register

Control

Logic

Reg.

20A(19:0)

RPS

C

C

CQ

9 CQ

9 9 Q[8:0]

Document #: 38-05619 Rev. *F Page 2 of 29

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