CY7C1345G
Document Number: 38-05517 Rev. *E Page 13 of 20

Timing Diagrams

Figure 1 shows the read cycle timing. [15]

Figure 1. Read Cycle Timing

tCYC
tCL
CLK
tADH
tADS
ADDRESS
tCH
tAH
tAS
A1
tCEH
tCES
Data Out (Q) High-Z
tCLZ
tDOH
tCDV
tOEHZ
tCDV
Single READ
BURST
READ
tOEV tOELZ tCHZ
Burst wraps around
to its initial state
tADVH
tADVS
tWEH
tWES
tADH
tADS
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1) Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
A2
ADV suspends burst
Deselect Cycle
DON’T CARE UNDEFINED
ADSP
ADSC
GW, BWE,BW
[A:B]
CE
ADV
OE
Note:
15.On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.