Timing Diagrams, Shows the read cycle timing

CY7C1345G

Timing Diagrams

Figure 1 shows the read cycle timing. [15]

Figure 1. Read Cycle Timing

tCYC

CLK

t CH

tADS tADH

ADSP

ADSC

tAS tAH

t CL

tADS tADH

ADDRESS

GW, BWE,BW

[A:B]

A1	A2
t WES	t WEH
tCES t CEH	Deselect Cycle
tCES t CEH
	t ADVS t ADVH

ADV
OE
		tOEV
		tOEHZ
		tCLZ
Data Out (Q)	High-Z	Q(A1)

tCDV

Single READ

ADV suspends burst

t	tCDV
	OELZ
	tCHZ
	tDOH

Q(A2)	Q(A2 + 1)	Q(A2 + 2)	Q(A2 + 3)	Q(A2)	Q(A2 + 1)	Q(A2 + 2)
				Burst wraps around
		BURST		to its initial state
		BURST
		READ
	DON’T CARE	UNDEFINED

Note:

15. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document Number: 38-05517 Rev. *E

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Cypress CY7C1345G manual Timing Diagrams, Shows the read cycle timing

CY7C1345G specifications

The Cypress CY7C1345G is a high-performance static random-access memory (SRAM) device designed for various applications requiring fast data access and minimal power consumption. As a member of Cypress's prolific family of SRAMs, the CY7C1345G is particularly noted for its performance in networking and telecommunications.

This device features a 512 Kbit (64 K x 8) memory organization, making it suitable for applications needing moderate amounts of fast-access memory. The CY7C1345G operates at a wide voltage range of 2.7V to 3.6V, accommodating both high-performance and low-power applications. One of its standout attributes is its fast access time, with read cycle times as low as 10 ns, allowing for rapid data retrieval that is essential for modern computing requirements.

Another key feature of the CY7C1345G is its low-power operation mode, making it an excellent choice for battery-operated applications. It has a typical active current of only 35 mA and a standby current of just 3 µA, ensuring prolonged battery life while still maintaining high-performance levels. This low power consumption is complemented by the device's sleep mode functionality, which further reduces power draw during periods of inactivity.

In terms of interface, the CY7C1345G employs a simple asynchronous access protocol, ensuring ease of integration into existing systems without the need for complex timing schemes. The device supports asynchronous read and write operations, with an output enable feature that facilitates efficient data retrieval.

The CY7C1345G is encased in a compact 44-pin TSOP II package, making it suitable for applications where space constraints are critical. Its design adheres to rigorous quality and reliability standards, with the device being fully tested to meet JEDEC specifications.

With its blend of speed, low power consumption, and simple interface, the Cypress CY7C1345G SRAM is ideal for a wide array of applications, including telecommunications systems, networking devices, and embedded systems. As technology drives the demand for faster and more efficient memory solutions, the CY7C1345G stands out as a reliable and versatile choice in the SRAM landscape.

Contents

Functional Description FeaturesSelection Guide Parameter 133 MHz 100 MHz Unit CLR Logic Block Diagram 15CY7C1345G Pin ConfigurationsPin Tqfp Pinout NC/576M Ball BGA PinoutNC/72M NC/36M Pin Definitions Functional Overview Operation. Mode Pin has an internal pull upStatic No Connects. Not Internally connected to the die Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical Characteristics Address Cycle Description Truth TableUsed Partial truth table for read or write follows Truth Table for Read or WriteFunction Maximum Ratings Electrical CharacteristicsOperating Range Range Ambient Thermal Resistance CapacitanceAC Test Loads and Waveforms Switching Characteristics Shows the read cycle timing Timing Diagrams Write Cycle Timing Read/Write Timing ZZ Mode Timing Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams 119-Ball BGA 14 x 22 x 2.4 mm Document History Issue Date Orig. Description of Change

Timing Diagrams

Figure 1 shows the read cycle timing. [15]

Figure 1. Read Cycle Timing

ADV

UNDEFINED

CY7C1345G specifications