Cypress CY7C1345G CY7C1345G

CY7C1345G

Document Number: 38-05517 Rev. *E Page 3 of 20

Pin Configurations

100-Pin TQFP Pinout

NC/72M

NC/36M

VSS

VDD

NC/9M

DQPB

DQB

VDDQ

VSSQ

DQB

VSSQ

VDDQ

DQB

VSS

VDD

DQA

VDDQ

VSSQ

DQA

VSSQ

VDDQ

DQA

DQPA

DQPC

DQC

VDDQ

VSSQ

DQC

VSSQ

VDDQ

DQC

VDD

VSS

DQD

VDDQ

VSSQ

DQD

VSSQ

VDDQ

DQD

DQPD

CE1

CE2

BWD

BWC

BWB

BWA

CE3

VDD

VSS

CLK

BWE

ADSP

100

BYTE A

BYTE C

ADV

ADSC

MODE

NC/18M

BYTE B

DQB

BYTE D

CY7C1345G

Contents

Main CY7C1345G 4-Mbit (128K x 36) Flow Through Sync SRAM Features Functional Description Selection Guide Document Number: 38-05517 Rev. *E Page 2 of 20 Logic Block Diagram ZZ MODE ADDRESS REGISTER BURST COUNTER AND LOGIC CLR Q1 Q0 CY7C1345G Document Number: 38-05517 Rev. *E Page 3 of 20 Pin Configurations CY7C1345G 100-Pin TQFP Pinout CY7C1345G Pin Configurations CY7C1345G Pin Definitions Functional Overview Single Read Accesses Single Write Accesses Initiated by ADSP Single Write Accesses Initiated by ADSC Pin Definitions CY7C1345G Burst Sequences Sleep Mode ZZ Mode Electrical Characteristics Truth Table Truth Table for Read or Write Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics CY7C1345G Timing Diagrams Figure 1 shows the read cycle timing. [15] Figure 1. Read Cycle Timing Figure 2 shows the write cycle timing. [15, 16] Figure 2. Write Cycle Timing Note: 16.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWx LOW. Figure 3 shows the read and write timing. [16, 17, 18] Figure 3. Read/Write Timing Figure 4 shows the ZZ mode timing. [19, 20] Figure 4. ZZ Mode Timing Ordering Information Package Diagrams Figure 5. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 A Figure 6. 119-Ball BGA (14 x 22 x 2.4 mm), 51-85115 Package Diagrams 51-85115-*B 0.900.05 0.56 Document History Page