Cypress CY7C1345G CY7C1345G

CY7C1345G

Document Number: 38-05517 Rev. *E Page 4 of 20

119-Ball BGA Pinout

Pin Configurations (continued)

2345671

VDDQ

NC/288M

NC/144M

DQPC

DQC

DQD

DQC

DQD

AA AA

ADSP VDDQ

CE2A

DQC

VDDQ

DQC

VDDQ

DQD

VDDQ

VDD

CLK

VDD

VSS

NC/576M

NC/1G

NCNCNCNC

NC/36MNC/72M

VDDQ

AAA

CE3

DQA

DQC

DQA

DQB

DQA

DQB

VDD

DQC

VDD

DQD

ADSC

CE1

ADV

VSS

VSS DQPA

MODE

DQPD

DQPB

BWB

BWC

NC VDD NC

BWA

BWE

BWD

Contents

Main CY7C1345G 4-Mbit (128K x 36) Flow Through Sync SRAM Features Functional Description Selection Guide Document Number: 38-05517 Rev. *E Page 2 of 20 Logic Block Diagram ZZ MODE ADDRESS REGISTER BURST COUNTER AND LOGIC CLR Q1 Q0 CY7C1345G Document Number: 38-05517 Rev. *E Page 3 of 20 Pin Configurations CY7C1345G 100-Pin TQFP Pinout CY7C1345G Pin Configurations CY7C1345G Pin Definitions Functional Overview Single Read Accesses Single Write Accesses Initiated by ADSP Single Write Accesses Initiated by ADSC Pin Definitions CY7C1345G Burst Sequences Sleep Mode ZZ Mode Electrical Characteristics Truth Table Truth Table for Read or Write Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics CY7C1345G Timing Diagrams Figure 1 shows the read cycle timing. [15] Figure 1. Read Cycle Timing Figure 2 shows the write cycle timing. [15, 16] Figure 2. Write Cycle Timing Note: 16.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWx LOW. Figure 3 shows the read and write timing. [16, 17, 18] Figure 3. Read/Write Timing Figure 4 shows the ZZ mode timing. [19, 20] Figure 4. ZZ Mode Timing Ordering Information Package Diagrams Figure 5. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 A Figure 6. 119-Ball BGA (14 x 22 x 2.4 mm), 51-85115 Package Diagrams 51-85115-*B 0.900.05 0.56 Document History Page