Cypress CY7C1345G Capacitance, Thermal Resistance

CY7C1345G

Document Number: 38-05517 Rev. *E Page 11 of 20

Capacitance

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions 100 TQFP

Max

119 BGA

Max Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VDD = 3.3V.

VDDQ = 3.3V

55pF

CCLK Clock Input Capacitance 5 5 pF

CIO Input or Output Capacitance 5 7 pF

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions 100 TQFP

Package

119 BGA

Package Unit

ΘJA Thermal Resistance

(Junction to Ambient)

Test conditions follow

standard test methods and

procedures for measuring

thermal impedance, per

EIA/JESD51.

30.32 34.1 °C/W

ΘJC Thermal Resistance

(Junction to Case)

6.85 14.0 °C/W

AC Test Loads and Waveforms

OUTPUT

R = 317Ω

R = 351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

V

T

= 1.5V

3.3V ALL INPUT PULSES

VDDQ

GND

90%

10%

90%

10%

≤1ns ≤1ns

(c)

OUTPUT

R = 1667Ω

R = 1538Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

VT= 1.25V

2.5V ALL INPUT PULSES

VDDQ

GND

90%

10%

90%

10%

≤1 ns ≤1 ns

(c)

3.3V I/O Test Load

2.5V I/O Test Load

Contents

Main CY7C1345G 4-Mbit (128K x 36) Flow Through Sync SRAM Features Functional Description Selection Guide Document Number: 38-05517 Rev. *E Page 2 of 20 Logic Block Diagram ZZ MODE ADDRESS REGISTER BURST COUNTER AND LOGIC CLR Q1 Q0 CY7C1345G Document Number: 38-05517 Rev. *E Page 3 of 20 Pin Configurations CY7C1345G 100-Pin TQFP Pinout CY7C1345G Pin Configurations CY7C1345G Pin Definitions Functional Overview Single Read Accesses Single Write Accesses Initiated by ADSP Single Write Accesses Initiated by ADSC Pin Definitions CY7C1345G Burst Sequences Sleep Mode ZZ Mode Electrical Characteristics Truth Table Truth Table for Read or Write Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics CY7C1345G Timing Diagrams Figure 1 shows the read cycle timing. [15] Figure 1. Read Cycle Timing Figure 2 shows the write cycle timing. [15, 16] Figure 2. Write Cycle Timing Note: 16.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWx LOW. Figure 3 shows the read and write timing. [16, 17, 18] Figure 3. Read/Write Timing Figure 4 shows the ZZ mode timing. [19, 20] Figure 4. ZZ Mode Timing Ordering Information Package Diagrams Figure 5. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 A Figure 6. 119-Ball BGA (14 x 22 x 2.4 mm), 51-85115 Package Diagrams 51-85115-*B 0.900.05 0.56 Document History Page