Cypress CY7C1345G Figure 3 shows the read and write timing. [16, 17, 18] Figure 3. Read/Write Timing

CY7C1345G
Document Number: 38-05517 Rev. *E Page 15 of 20
Figure 3 shows the read and write timing. [16, 17, 18]
Figure 3. Read/Write Timing
Timing Diagrams (continued)
tCYC
tCL
CLK
tADH
tADS
ADDRESS
tCH
tAH
tAS
A2
tCEH
tCES
Single WRITE
D(A3)
A3 A4
BURST READ Back-to-Back READs
High-Z
Q(A2) Q(A4) Q(A4+1)
Q(A4+2) Q(A4+3)
tWEH
tWES
tOEHZ
tDH
tDS
tCDV
tOELZ
A1 A5 A6
D(A5) D(A6)
Q(A1)
Back-to-Back
WRITEs
DON’T CARE UNDEFINED
ADSP
ADSC
BWE, BW [A:B]
CE
ADV
OE
Data In (D)
Data Out (Q)
Notes:
17.The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
18.GW is HIGH.