Read/Write Timing | Cypress CY7C1345G manual

CY7C1345G

Timing Diagrams (continued)

Figure 3 shows the read and write timing. [16, 17, 18]

Figure 3. Read/Write Timing

tCYC

CLK

ADSP

ADSC

tCH tCL

tADS tADH

ADDRESS

BWE, BW [A:B]

ADV

Data In (D)

Data Out (Q)

tAS tAH

A1	A2	A3	A4
		tWES	tWEH
	tCES	tCEH

tDS	tDH
	tOELZ

High-Z	t	D(A3)
	OEHZ	tCDV
		tCDV
Q(A1)	Q(A2)	Q(A4)	Q(A4+1)	Q(A4+2)	Q(A4+3)
Back-to-Back READs		Single WRITE	BURST READ
		DON’T CARE	UNDEFINED

A5 A6

D(A5) D(A6)

Back-to-Back

WRITEs

Notes:

17.The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

18.GW is HIGH.

Document Number: 38-05517 Rev. *E

Page 15 of 20

Page 15

Image 15

Cypress CY7C1345G manual Read/Write Timing

CY7C1345G specifications

The Cypress CY7C1345G is a high-performance static random-access memory (SRAM) device designed for various applications requiring fast data access and minimal power consumption. As a member of Cypress's prolific family of SRAMs, the CY7C1345G is particularly noted for its performance in networking and telecommunications.

This device features a 512 Kbit (64 K x 8) memory organization, making it suitable for applications needing moderate amounts of fast-access memory. The CY7C1345G operates at a wide voltage range of 2.7V to 3.6V, accommodating both high-performance and low-power applications. One of its standout attributes is its fast access time, with read cycle times as low as 10 ns, allowing for rapid data retrieval that is essential for modern computing requirements.

Another key feature of the CY7C1345G is its low-power operation mode, making it an excellent choice for battery-operated applications. It has a typical active current of only 35 mA and a standby current of just 3 µA, ensuring prolonged battery life while still maintaining high-performance levels. This low power consumption is complemented by the device's sleep mode functionality, which further reduces power draw during periods of inactivity.

In terms of interface, the CY7C1345G employs a simple asynchronous access protocol, ensuring ease of integration into existing systems without the need for complex timing schemes. The device supports asynchronous read and write operations, with an output enable feature that facilitates efficient data retrieval.

The CY7C1345G is encased in a compact 44-pin TSOP II package, making it suitable for applications where space constraints are critical. Its design adheres to rigorous quality and reliability standards, with the device being fully tested to meet JEDEC specifications.

With its blend of speed, low power consumption, and simple interface, the Cypress CY7C1345G SRAM is ideal for a wide array of applications, including telecommunications systems, networking devices, and embedded systems. As technology drives the demand for faster and more efficient memory solutions, the CY7C1345G stands out as a reliable and versatile choice in the SRAM landscape.

Contents

Parameter 133 MHz 100 MHz Unit FeaturesFunctional Description Selection Guide CLR Logic Block Diagram Pin Configurations 15CY7C1345GPin Tqfp Pinout Ball BGA Pinout NC/576MNC/72M NC/36M Pin Definitions No Connects. Not Internally connected to the die Operation. Mode Pin has an internal pull upFunctional Overview Static Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical Characteristics Truth Table Address Cycle DescriptionUsed Truth Table for Read or Write Partial truth table for read or write followsFunction Range Ambient Electrical CharacteristicsMaximum Ratings Operating Range Capacitance Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Shows the read cycle timing Timing Diagrams Write Cycle Timing Read/Write Timing ZZ Mode Timing Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams 119-Ball BGA 14 x 22 x 2.4 mm Document History Issue Date Orig. Description of Change