Write Cycle Timing | Cypress CY7C1345G guide

CY7C1345G

Timing Diagrams (continued)

Figure 2 shows the write cycle timing. [15, 16]

Figure 2. Write Cycle Timing

	t CYC
CLK	t CL
t CH	t CL

tADS tADH

ADSP

tADS	tADH	ADSC extends burst
		tADS	tADH

ADSC

tAS tAH

ADDRESS

BWE,

BW[A:B]

Byte write signals are ignored for first cycle when

ADSP initiates burst

t t

WES WEH

tWES tWEH

tCES tCEH

ADV

Data in (D)

High-Z

Data Out (Q)

BURST READ

							tADVS tADVH
			ADV suspends burst
t DS t DH
D(A1)	D(A2)	D(A2 + 1)	D(A2 + 1)	D(A2 + 2)	D(A2 + 3)	D(A3)	D(A3 + 1)	D(A3 + 2)
tOEHZ
Single WRITE		BURST WRITE					Extended BURST WRITE
		DON’T CARE	UNDEFINED

Note:

16. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWx LOW.

Document Number: 38-05517 Rev. *E

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Cypress CY7C1345G manual Write Cycle Timing

CY7C1345G specifications

The Cypress CY7C1345G is a high-performance static random-access memory (SRAM) device designed for various applications requiring fast data access and minimal power consumption. As a member of Cypress's prolific family of SRAMs, the CY7C1345G is particularly noted for its performance in networking and telecommunications.

This device features a 512 Kbit (64 K x 8) memory organization, making it suitable for applications needing moderate amounts of fast-access memory. The CY7C1345G operates at a wide voltage range of 2.7V to 3.6V, accommodating both high-performance and low-power applications. One of its standout attributes is its fast access time, with read cycle times as low as 10 ns, allowing for rapid data retrieval that is essential for modern computing requirements.

Another key feature of the CY7C1345G is its low-power operation mode, making it an excellent choice for battery-operated applications. It has a typical active current of only 35 mA and a standby current of just 3 µA, ensuring prolonged battery life while still maintaining high-performance levels. This low power consumption is complemented by the device's sleep mode functionality, which further reduces power draw during periods of inactivity.

In terms of interface, the CY7C1345G employs a simple asynchronous access protocol, ensuring ease of integration into existing systems without the need for complex timing schemes. The device supports asynchronous read and write operations, with an output enable feature that facilitates efficient data retrieval.

The CY7C1345G is encased in a compact 44-pin TSOP II package, making it suitable for applications where space constraints are critical. Its design adheres to rigorous quality and reliability standards, with the device being fully tested to meet JEDEC specifications.

With its blend of speed, low power consumption, and simple interface, the Cypress CY7C1345G SRAM is ideal for a wide array of applications, including telecommunications systems, networking devices, and embedded systems. As technology drives the demand for faster and more efficient memory solutions, the CY7C1345G stands out as a reliable and versatile choice in the SRAM landscape.

Contents

Selection Guide FeaturesFunctional Description Parameter 133 MHz 100 MHz Unit Logic Block Diagram CLR Pin Tqfp Pinout Pin Configurations15CY7C1345G NC/72M NC/36M Ball BGA PinoutNC/576M Pin Definitions Static Operation. Mode Pin has an internal pull upFunctional Overview No Connects. Not Internally connected to the die ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Used Truth TableAddress Cycle Description Function Truth Table for Read or WritePartial truth table for read or write follows Operating Range Electrical CharacteristicsMaximum Ratings Range Ambient AC Test Loads and Waveforms CapacitanceThermal Resistance Switching Characteristics Timing Diagrams Shows the read cycle timing Write Cycle Timing Read/Write Timing ZZ Mode Timing Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm 119-Ball BGA 14 x 22 x 2.4 mm Issue Date Orig. Description of Change Document History