Cypress CY7C1356C, CY7C1354C manual Switching Characteristics Over the Operating Range 18

CY7C1354C

CY7C1356C

Switching Characteristics Over the Operating Range [18, 19]

								–250		–200		–166
Parameter							Description							Unit
								Min.	Max.	Min.	Max.	Min.	Max.
tPower[17]	VCC (typical) to the First Access Read or Write							1		1		1		ms
Clock
tCYC	Clock Cycle Time							4.0		5		6		ns
FMAX	Maximum Operating Frequency								250		200		166	MHz
tCH	Clock HIGH							1.8		2.0		2.4		ns
tCL	Clock LOW							1.8		2.0		2.4		ns
tEOV		LOW to Output Valid							2.8		3.2		3.5	ns
	OE
tCLZ	Clock to Low-Z[20, 21, 22]							1.25		1.5		1.5		ns
Output Times
tCO	Data Output Valid after CLK Rise								2.8		3.2		3.5	ns
tEOV		LOW to Output Valid							2.8		3.2		3.5	ns
	OE
tDOH	Data Output Hold after CLK Rise							1.25		1.5		1.5		ns
tCHZ	Clock to High-Z[20, 21, 22]							1.25	2.8	1.5	3.2	1.5	3.5	ns
tCLZ	Clock to Low-Z[20, 21, 22]							1.25		1.5		1.5		ns
tEOHZ		HIGH to Output High-Z[20, 21, 22]							2.8		3.2		3.5	ns
	OE
tEOLZ		LOW to Output Low-Z[20, 21, 22]						0		0		0		ns
	OE
Set-up Times
tAS	Address Set-up before CLK Rise							1.4		1.5		1.5		ns
tDS	Data Input Set-up before CLK Rise							1.4		1.5		1.5		ns
tCENS					Set-up before CLK Rise			1.4		1.5		1.5		ns
	CEN
tWES							x Set-up before CLK Rise	1.4		1.5		1.5		ns
	WE,			BW
tALS
	ADV/LD					Set-up before CLK Rise		1.4		1.5		1.5		ns
tCES	Chip Select Set-up							1.4		1.5		1.5		ns
Hold Times
tAH	Address Hold after CLK Rise							0.4		0.5		0.5		ns
tDH	Data Input Hold after CLK Rise							0.4		0.5		0.5		ns
tCENH			Hold after CLK Rise					0.4		0.5		0.5		ns
	CEN
tWEH		,					x Hold after CLK Rise	0.4		0.5		0.5		ns
	WE			BW
tALH
	ADV/LD					Hold after CLK Rise		0.4		0.5		0.5		ns
tCEH	Chip Select Hold after CLK Rise							0.4		0.5		0.5		ns

Notes:

17.This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be initiated.

18.Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

19.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

20.tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

21.At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

22.This parameter is sampled and not 100% tested.

Document #: 38-05538 Rev. *G Page 19 of 28

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