CY7C1354C

CY7C1356C

Because the CY7C1354C and CY7C1356C are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1354C and DQa,b/DQPa,b for CY7C1356C) inputs. Doing so will tri-state the output drivers. As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for CY7C1354C and DQa,b/DQPa,b for CY7C1356C) are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1354C/CY7C1356C has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subse- quent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BWa,b,c,d for CY7C1354C and BWa,b for CY7C1356C) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW.

Interleaved Burst Address Table (MODE = Floating or VDD)

First

Second

Third

Fourth

Address

Address

Address

Address

A1,A0

A1,A0

A1,A0

A1,A0

00

01

10

11

01

00

11

10

10

11

00

01

11

10

01

00

Linear Burst Address Table (MODE = GND)

First

Second

Third

Fourth

Address

Address

Address

Address

A1,A0

A1,A0

A1,A0

A1,A0

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min.

Max.

Unit

IDDZZ

Sleep mode standby current

ZZ > VDD 0.2V

 

50

mA

tZZS

Device operation to ZZ

ZZ > VDD 0.2V

 

2tCYC

ns

tZZREC

ZZ recovery time

ZZ < 0.2V

2tCYC

 

ns

tZZI

ZZ active to sleep current

This parameter is sampled

 

2tCYC

ns

tRZZI

ZZ Inactive to exit sleep current

This parameter is sampled

0

 

ns

Truth Table[2, 3, 4, 5, 6, 7, 8]

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operation

Used

 

CE

 

ZZ

 

ADV/LD

 

WE

 

 

BWx

 

 

OE

 

 

CEN

 

CLK

DQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle

None

 

H

 

L

 

L

 

X

 

X

 

X

 

 

L

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Continue Deselect Cycle

None

 

X

 

L

 

H

 

X

 

X

 

X

 

 

L

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle (Begin Burst)

External

 

L

 

L

 

L

 

H

 

X

 

L

 

 

L

L-H

Data Out (Q)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle (Continue Burst)

Next

 

X

 

L

 

H

 

X

 

X

 

L

 

 

L

L-H

Data Out (Q)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOP/Dummy Read (Begin Burst)

External

 

L

 

L

 

L

 

H

 

X

 

H

 

 

L

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dummy Read (Continue Burst)

Next

 

X

 

L

 

H

 

X

 

X

 

H

 

 

L

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle (Begin Burst)

External

 

L

 

L

 

L

 

L

 

L

 

X

 

 

L

L-H

Data In (D)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle (Continue Burst)

Next

 

X

 

L

 

H

 

X

 

L

 

X

 

 

L

L-H

Data In (D)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

2.X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.

3.Write is defined by WE and BWX. See Write Cycle Description table for details.

4.When a write cycle is detected, all I/Os are tri-stated, even during Byte Writes.

5.The DQ and DQP pins are controlled by the current cycle and the OE signal.

6.CEN = H inserts wait states.

7.Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.

8.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE is inactive or when the device is deselected, and DQs = data when OE is active.

Document #: 38-05538 Rev. *G

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Cypress CY7C1354C, CY7C1356C Interleaved Burst Address Table Mode = Floating or VDD, Linear Burst Address Table Mode = GND