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Cypress CY7C1357C manual Pin Configurations Pin Tqfp Pinout, CY7C1355C

Models: CY7C1355C CY7C1357C

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CY7C1355C

CY7C1357C

Pin Configurations

100-Pin TQFP Pinout

BYTE C

BYTE D

DQPC

DQC

VDDQ

VSS

DQC

VSS

VDDQ

DQC DQC

Vss/DNU

VDD

VSS

DQD

VDDQ

VSS

DQD

VSS

VDDQ

DQD

DQPD

A		A		CE	CE	BW		BW	BW	BW		CE	V		V		CLK		WE	CEN	OE		ADV/LD		NC/18M		A		A	A
A		A		CE	CE	BW		BW	BW	BW		CE	V		V		CLK		WE	CEN	OE		ADV/LD		NC/18M		A		A	A
				1	2		D	C	B	A	3			DD		SS
														DD		SS



100		99		98	97	96		95	94	93	92		91		90		89		88	87	86	85			84		83		82	81
1																														80
2																														79
3																														78
4																														77
5																														76
6																														75
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13											CY7C1355C																			68
14											CY7C1355C																			67
14																														67
15																														66
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31		32		33	34	35		36	37	38	39		40		41		42		43	44	45	46			47		48		49	50


	MODE		A	A	A	A		A1	A0	NC/288M		NC/144M		SS		DD		NC/72M	NC/36M	A	A			A		A		A	A		A
	MODE		A	A	A	A		A1	A0	NC/288M		NC/144M		V		V		NC/72M	NC/36M	A	A			A		A		A	A		A

DQPB

DQB DQB

VDDQ

VSS

DQB DQB DQB DQB

VSS

VDDQ

DQB DQB

VSS

VDD

DQA DQA

VDDQ

VSS

DQA DQA DQA DQA

VSS

VDDQ

DQA DQA DQPA

BYTE B

BYTE A

Document #: 38-05539 Rev. *E

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Cypress CY7C1357C manual Pin Configurations Pin Tqfp Pinout, CY7C1355C

Contents

133 MHz 100 MHz Unit FeaturesFunctional Description1 Selection GuideLogic Block Diagram CY7C1357C 512K x Logic Block Diagram CY7C1355C 256K xCY7C1355C Pin Configurations Pin Tqfp PinoutCY7C1357C Pin Configurations Ball BGA Pinout 3 Chip Enables with Jtag Pin Configurations Ball Fbga Pinout 3 Chip enable with Jtag CE2 CLKCE2 Name Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Pin DefinitionsFunctional Overview Single Read AccessesBurst Read Accesses Single Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1355C Sleep ModePartial Truth Table for Read/Write2, 3 Truth Table for Read/Write2, 3,9TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterSet-up Times TAP TimingParameter Description Min Max Unit Clock Output TimesIdentification Register Definitions 3V TAP AC Test Conditions5V TAP AC Test Conditions 5V TAP AC Output Load EquivalentInstruction Code Description Scan Register SizesIdentification Codes Register Name Bit SizeName CY7C1355C 256K x Bit# Ball ID SignalCY7C1357C 512K x Bit# Ball Id Signal Name Ball BGA Boundary Scan OrderCY7C1355C 256K x Bit# Ball ID Signal Name Ball Fbga Boundary Scan OrderBWD Ambient Range Electrical Characteristics Over the Operating Range13Maximum Ratings Operating Range3V I/O Test Load Capacitance15Thermal Resistance15 AC Test Loads and Waveforms100 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 16Write Switching WaveformsCommand Read/Write Waveforms22, 23QA4+1 DA5 QA6 DA7 NOP, Stall and Deselect Cycles22, 23ZZ Mode Timing26 Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams90±0.05 Ball BGA 14 x 22 x 2.4 mmSoldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change