Cypress CY7C1480V25, CY7C1486V25, CY7C1482V25 manual Pin Definitions

											CY7C1480V25
											CY7C1482V25
											CY7C1486V25
Pin Definitions
	Pin Name							I/O	Description
	A0, A1, A							Input-	Address Inputs used to select one of the address locations. Sampled at the rising
								Synchronous	edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled
									active. A1: A0 are fed to the two-bit counter.
			A,		B,		C,	Input-	Byte Write Select Inputs, active LOW. Qualified with		to conduct byte writes to the
	BW			BW		BW				BWE
	BWD, BWE, BWF,							Synchronous	SRAM. Sampled on the rising edge of CLK.
	BWG, BWH
								Input-	Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK,
	GW
								Synchronous	a global write is conducted (ALL bytes are written, regardless of the values on BWX and
									BWE).
								Input-	Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
	BWE
								Synchronous	must be asserted LOW to conduct a byte write.
	CLK							Input-	Clock Input. Captures all synchronous inputs to the device. Also increments the burst
								Clock	counter when ADV is asserted LOW during a burst operation.
		1						Input-	Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
	CE
								Synchronous	conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is
									HIGH. CE1 is sampled only when a new external address is loaded.
	CE2							Input-	Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
								Synchronous	conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a
									new external address is loaded.
		3						Input-	Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
	CE
								Synchronous	conjunction with CE1 and CE2 to select/deselect the device. CE3 is sampled only when a
									new external address is loaded.
								Input-	Output Enable, asynchronous input, active LOW. Controls the direction of the IO pins.
	OE
								Asynchronous	When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated,
									and act as input data pins. OE is masked during the first clock of a read cycle when
									emerging from a deselected state.
								Input-	Advance Input signal, sampled on the rising edge of CLK, active LOW. When
	ADV
								Synchronous	asserted, it automatically increments the address in a burst cycle.
								Input-	Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
	ADSP
								Synchronous	When asserted LOW, addresses presented to the device are captured in the address
									registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
									asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
								Input-	Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
	ADSC
								Synchronous	When asserted LOW, addresses presented to the device are captured in the address
									registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
									asserted, only ADSP is recognized.
	ZZ							Input-	ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
								Asynchronous	non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
									pin has to be LOW or left floating. ZZ pin has an internal pull down.
	DQs, DQPs							I/O-	Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is
								Synchronous	triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
									memory location specified by the addresses presented during the previous clock rise of
									the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,
									the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.
	VDD							Power Supply	Power supply inputs to the core of the device.
	VSS							Ground	Ground for the core of the device.
	VSSQ[2]							I/O Ground	Ground for the I/O circuitry.
	VDDQ							I/O Power Supply	Power supply for the I/O circuitry.

Note

2. Applicable for TQFP package. For BGA package VSS serves as ground for the core and the IO circuitry.

Document #: 38-05282 Rev. *H Page 7 of 32

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