Cypress CY7C1486V25 manual Switching Characteristics Over the Operating Range15, Setup Times

CY7C1480V25

CY7C1482V25

CY7C1486V25

Switching Characteristics Over the Operating Range[15, 16]

Parameter										Description	250 MHz		200 MHz		167 MHz		Unit
											Min.	Max.	Min.	Max.	Min.	Max.
tPOWER	VDD(Typical) to the first access[17]										1		1		1		ms
Clock
tCYC	Clock Cycle Time										4.0		5.0		6.0		ns
tCH	Clock HIGH										2.0		2.0		2.4		ns
tCL	Clock LOW										2.0		2.0		2.4		ns
Output Times
tCO	Data Output Valid After CLK Rise											3.0		3.0		3.4	ns
tDOH	Data Output Hold After CLK Rise										1.3		1.3		1.5		ns
t	Clock to Low-Z[18, 19, 20]										1.3		1.3		1.5		ns
CLZ
t	Clock to High-Z[18, 19, 20]											3.0		3.0		3.4	ns
CHZ
tOEV		LOW to Output Valid										3.0		3.0		3.4	ns
	OE
tOELZ		LOW to Output Low-Z[18, 19, 20]									0		0		0		ns
	OE
tOEHZ		HIGH to Output High-Z[18, 19, 20]										3.0		3.0		3.4	ns
	OE
Setup Times
tAS	Address Setup Before CLK Rise										1.4		1.4		1.5		ns
tADS									Setup Before CLK Rise		1.4		1.4		1.5		ns
	ADSC,					ADSP
tADVS				Setup Before CLK Rise							1.4		1.4		1.5		ns
	ADV
tWES										X Setup Before CLK Rise	1.4		1.4		1.5		ns
	GW,			BWE,			BW
tDS	Data Input Setup Before CLK Rise										1.4		1.4		1.5		ns
tCES	Chip Enable Setup Before CLK Rise										1.4		1.4		1.5		ns
Hold Times
tAH	Address Hold After CLK Rise										0.4		0.4		0.5		ns
tADH								Hold After CLK Rise			0.4		0.4		0.5		ns
	ADSP,				ADSC
tADVH			Hold After CLK Rise								0.4		0.4		0.5		ns
	ADV
tWEH										X Hold After CLK Rise	0.4		0.4		0.5		ns
	GW,			BWE,			BW
tDH	Data Input Hold After CLK Rise										0.4		0.4		0.5		ns
tCEH	Chip Enable Hold After CLK Rise										0.4		0.4		0.5		ns

Notes

15.Timing reference level is 1.25V when VDDQ = 2.5V and is 0.9V when VDDQ = 1.8V.

16.Test conditions shown in (a) of “AC Test Loads and Waveforms” on page 20 unless otherwise noted.

17.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated.

18.tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms. Transition is measured ±200 mV from steady-state voltage.

19.At any possible voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z before Low-Z under the same system conditions.

20.This parameter is sampled and not 100% tested.

Document #: 38-05282 Rev. *H Page 21 of 32

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