Cypress CY7C1480V25, CY7C1486V25, CY7C1482V25 manual Maximum Ratings, Operating Range, Range Ambient

CY7C1480V25

CY7C1482V25

CY7C1486V25

Maximum Ratings

Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature		–65°C to +150°C
Ambient Temperature with
Power Applied		–55°C to +125°C
Supply Voltage on VDD Relative to GND		–0.3V to +3.6V
Supply Voltage on VDDQ Relative to GND		–0.3V to +VDD
DC Voltage Applied to Outputs	–0.5V to VDDQ + 0.5V
in Tri-State

DC Input Voltage		–0.5V to VDD + 0.5V
Current into Outputs (LOW)			20 mA
Static Discharge Voltage			>2001V
(MIL-STD-883, Method 3015)
Latch Up Current			>200 mA
Operating Range
Range	Ambient	VDD	VDDQ
	Temperature
Commercial	0°C to +70°C	2.5V –5%/+5%	1.7V to
			VDD
Industrial	–40°C to +85°C

Electrical Characteristics Over the Operating Range[12, 13]

Parameter	Description	Test Conditions		Min	Max	Unit
VDD	Power Supply Voltage			2.375	2.625	V
VDDQ	IO Supply Voltage	for 2.5V IO		2.375	VDD	V
		for 1.8V IO		1.7	1.9	V
VOH	Output HIGH Voltage	for 2.5V IO, IOH = –1.0 mA		2.0		V
		for 1.8V IO, IOH = –100 ∝A		1.6		V
VOL	Output LOW Voltage	for 2.5V IO, IOL = 1.0 mA			0.4	V
		for 1.8V IO, IOL = 100 ∝A			0.2	V
VIH	Input HIGH Voltage[12]	for 2.5V IO		1.7	VDD + 0.3V	V
		for 1.8V IO		1.26	VDD + 0.3V	V
VIL	Input LOW Voltage[12]	for 2.5V IO		–0.3	0.7	V
		for 1.8V IO		–0.3	0.36	V
IX	Input Leakage Current	GND ≤ VI ≤ VDDQ		–5	5	∝A
	except ZZ and MODE
	Input Current of MODE	Input = VSS		–30		∝A
		Input = VDD			5	∝A
	Input Current of ZZ	Input = VSS		–5		∝A
		Input = VDD			30	∝A
IOZ	Output Leakage Current	GND ≤ VI ≤ VDDQ, Output Disabled		–5	5	∝A
IDD	VDD Operating Supply	VDD = Max., IOUT = 0 mA,	4.0-ns cycle, 250 MHz		450	mA
	Current	f = fMAX = 1/tCYC
			5.0-ns cycle, 200 MHz		450	mA
			6.0-ns cycle, 167 MHz		400	mA
ISB1	Automatic CE	VDD = Max, Device Deselected,	4.0-ns cycle, 250 MHz		200	mA
	Power Down	VIN ≥ VIH or VIN ≤ VIL
			5.0-ns cycle, 200 MHz		200	mA
	Current—TTL Inputs	f = fMAX = 1/tCYC
			6.0-ns cycle, 167 MHz		200	mA
ISB2	Automatic CE	VDD = Max, Device Deselected,	All speeds		120	mA
	Power Down	VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
	Current—CMOS Inputs	f = 0
ISB3	Automatic CE	VDD = Max, Device Deselected, or	4.0-ns cycle, 250 MHz		200	mA
	Power Down	VIN ≤ 0.3V or VIN > VDDQ – 0.3V
			5.0-ns cycle, 200 MHz		200	mA
	Current—CMOS Inputs	f = fMAX = 1/tCYC
			6.0-ns cycle, 167 MHz		200	mA
ISB4	Automatic CE	VDD = Max, Device Deselected,	All speeds		135	mA
	Power Down	VIN ≥ VIH or VIN ≤ VIL, f = 0
	Current—TTL Inputs
Notes

12.Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).

13.Power up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

Document #: 38-05282 Rev. *H Page 19 of 32

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