Cypress CY7C1392CV18, CY7C1393CV18, CY7C1394CV18, CY7C1992CV18 CY7C1392CV18, CY7C1992CV18

CY7C1392CV18, CY7C1992CV18
CY7C1393CV18, CY7C1394CV18
Document #: 001-07162 Rev. *C Page 2 of 30
Logic Block Diagram (CY7C1392CV18)
Logic Block Diagram (CY7C1992CV18)
1M x 8 Array
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Add. Decode
Read Data Reg.
LD Q[7:0]
Reg.
Reg.
Reg.
8
8
16
8
NWS[1:0]
VREF
Write Add. Decode
Write
Data Reg
88
20
8
R/W
LD
R/W
CQ
CQ
DOFF
1M x 8 Array
Write
Data Reg
Control
Logic
C
C
1M x 9 Array
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Add. Decode
Read Data Reg.
LD Q[8:0]
Reg.
Reg.
Reg.
9
18
9
BWS[0]
VREF
Write Add. Decode
Write
Data Reg
99
20
9
R/W
LD
R/W
CQ
CQ
DOFF
1M x 9 Array
Write
Data Reg
Control
Logic
C
C
9
[+] Feedback