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Cypress CY7C1392CV18, CY7C1992CV18 TAP Controller Block Diagram, TAP Electrical Characteristics

Models: CY7C1394CV18 CY7C1392CV18 CY7C1393CV18 CY7C1992CV18

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CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18

TAP Controller Block Diagram


																						0
																						0

																			Bypass Register

TDI						Selection													2	1		0						Selection
																			2	1		0

														Instruction Register
						Circuitry								Instruction Register
																												Circuitry
												31		30	29	.	.		2	1		0						Circuitry



														Identification Register

												106		.	.	.	.		2	1		0



														Boundary Scan Register

	TCK

																TAP Controller

	TMS
	TMS

TDO

TAP Electrical Characteristics

Over the Operating Range [10, 11, 12]

Parameter	Description	Test Conditions	Min	Max	Unit
VOH1	Output HIGH Voltage	IOH = −2.0 mA	1.4		V
VOH2	Output HIGH Voltage	IOH = −100 μA	1.6		V
VOL1	Output LOW Voltage	IOL = 2.0 mA		0.4	V
VOL2	Output LOW Voltage	IOL = 100 μA		0.2	V
VIH	Input HIGH Voltage		0.65VDD	VDD + 0.3	V
VIL	Input LOW Voltage		–0.3	0.35VDD	V
IX	Input and Output Load Current	GND ≤ VI ≤ VDD	–5	5	μA

Notes

10.These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.

11.Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −1.5V (Pulse width less than tCYC/2).

12.All Voltage referenced to Ground.

Document #: 001-07162 Rev. *C

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Cypress CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, CY7C1394CV18 TAP Controller Block Diagram, TAP Electrical Characteristics

Contents

Selection Guide FeaturesConfigurations Functional Description Logic Block Diagram CY7C1392CV18 CLKDoff Array Gen Read Data Reg Control Logic Block Diagram CY7C1393CV18Logic Block Diagram CY7C1394CV18 512K CY7C1992CV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1392CV18 2M x CY7C1394CV18 512K x CY7C1393CV18 1M x Pin Definitions Pin Name Pin DescriptionSynchronous Read/Write input. When TDO for Jtag Power supply inputs to the core of the devicePower supply inputs for the outputs of the device Is referenced with respect to Functional Overview Shows four DDR-II SIO used in an application Application Example Comments Truth TableWrite Cycle Descriptions Operation Into the device. D359 remains unaltered Write cycle description table for CY7C1992CV18 followsWrite cycle description table for CY7C1394CV18 follows Device Ieee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block Diagram TAP Timing and Test Conditions TAP AC Switching Characteristics Register Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction Codes Bit # Bump ID Boundary Scan Order Power Up Sequence in DDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Input High Voltage Vref +Input LOW Voltage Vref Document # 001-07162 Rev. *C Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max Unit LOW Switching CharacteristicsParameter Min Max High DLL Timing Parameter Min Max Output Times Burst Switching Waveforms Ordering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package Diagram Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsDocument History