250 | Cypress CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, CY7C1394CV18

CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Ordering Information (continued)

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
250	CY7C1392CV18-250BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1992CV18-250BZC

	CY7C1393CV18-250BZC

	CY7C1394CV18-250BZC

	CY7C1392CV18-250BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1992CV18-250BZXC

	CY7C1393CV18-250BZXC

	CY7C1394CV18-250BZXC

	CY7C1392CV18-250BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1992CV18-250BZI

	CY7C1393CV18-250BZI

	CY7C1394CV18-250BZI

	CY7C1392CV18-250BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1992CV18-250BZXI

	CY7C1393CV18-250BZXI

	CY7C1394CV18-250BZXI

200	CY7C1392CV18-200BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1992CV18-200BZC

	CY7C1393CV18-200BZC

	CY7C1394CV18-200BZC

	CY7C1392CV18-200BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1992CV18-200BZXC

	CY7C1393CV18-200BZXC

	CY7C1394CV18-200BZXC

	CY7C1392CV18-200BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1992CV18-200BZI

	CY7C1393CV18-200BZI

	CY7C1394CV18-200BZI

	CY7C1392CV18-200BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1992CV18-200BZXI

	CY7C1393CV18-200BZXI

	CY7C1394CV18-200BZXI

Document #: 001-07162 Rev. *C

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Cypress CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, CY7C1394CV18 manual 250

Contents

Selection Guide FeaturesConfigurations Functional Description Logic Block Diagram CY7C1392CV18 CLKDoff Array Gen Read Data Reg Control Logic Block Diagram CY7C1393CV18Logic Block Diagram CY7C1394CV18 512K CY7C1992CV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1392CV18 2M x CY7C1394CV18 512K x CY7C1393CV18 1M x Pin Definitions Pin Name Pin DescriptionSynchronous Read/Write input. When TDO for Jtag Power supply inputs to the core of the devicePower supply inputs for the outputs of the device Is referenced with respect to Functional Overview Shows four DDR-II SIO used in an application Application Example Comments Truth TableWrite Cycle Descriptions Operation Into the device. D359 remains unaltered Write cycle description table for CY7C1992CV18 followsWrite cycle description table for CY7C1394CV18 follows Device Ieee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block Diagram TAP Timing and Test Conditions TAP AC Switching Characteristics Register Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction Codes Bit # Bump ID Boundary Scan Order Power Up Sequence in DDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Input High Voltage Vref +Input LOW Voltage Vref Document # 001-07162 Rev. *C Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max Unit LOW Switching CharacteristicsParameter Min Max High DLL Timing Parameter Min Max Output Times Burst Switching Waveforms Ordering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package Diagram Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsDocument History