CY7C1392CV18, CY7C1992CV18CY7C1393CV18, CY7C1394CV18
Document #: 001-07162 Rev. *C Page 7 of 30
CQ Echo Clock CQ is referenced with respect to C. This is a free-running clock and is synchronized to the input clock
for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks is shown in the Switching Characteristics on page 23.
CQ Echo Clock CQ is referenced with respect to C. This is a free-running clock and is synchronized to the input clock
for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks is shown in the Switching Characteristics on page 23.
ZQ Input Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left uncon-
nected.
DOFF Input DLL turn off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing
in the DLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull up through a 10-Kohm or less pull up resistor. The device behaves in DDR-I
mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167
MHz with DDR-I timing.
TDO Output TDO for JTAG.
TCK Input TCK pin for JTAG.
TDI Input TDI pin for JT AG.
TMS Input TMS pin for JTAG.
NC N/A Not connected to the die. Can be tied to any voltage level.
NC/36M N/A Not connected to the die. Can be tied to any voltage level.
NC/72M N/A Not connected to the die. Can be tied to any voltage level.
NC/144M N/A Not connected to the die. Can be tied to any voltage level.
NC/288M N/A Not connected to the die. Can be tied to any voltage level.
VREF Input-
Reference Reference Voltage input. Static input used to set the reference level for HSTL inputs, Outputs, and AC
measurement points.
VDD Power Supply Power supply inputs to the core of the device.
VSS Ground Ground for the device.
VDDQ Power Supply Power supply inputs for the outputs of the device.
Pin Definitions (continued)
Pin Name IO Pin Description
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