Document #: 001-07162 Rev. *C Revised May 22, 2008 Page 30 of 30
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CY7C1392CV18, CY7C1992CV18
CY7C1393CV18, CY7C1394CV18
© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
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for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement w i th Cy press. Furthermore, Cypress does not authorize its products for use
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Document History Page
Document Title: CY7C1392CV18/CY7C1992CV18/CY7C1393CV18/CY7C1394CV18, 18-Mbit DDR-II SIO SRAM 2-Word
Burst Architecture
Document Number: 001-07162
Rev. ECN No. Submission
Date Orig. of
Change Description of Change
** 433284 See ECN NXR New data sheet
*A 462615 See ECN NXR Changed tCYC from 100 ns to 50 ns, changed tTH and tTL from 40 ns to 20 ns, changed
tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns
to 10 ns in TAP AC Switching Characteristics table
Modified Power-Up waveform
*B 1523386 See ECN VKN/AESA Converted from preliminary to final, Updated Logic Block diagram, Updated IDD/ISB
specs, Changed DLL minimum operating frequency from 80MHz to 120MHz, Changed
tCYC max spec to 8.4ns for all speed bins, Modified footnotes 20 and 28.
*C 2507766 05/23/08 VKN/PYRS Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to “–55°C
to +125°C” in the “Maximum Ratings“ on page 20, Updated power up sequence
waveform and its description, Added footnote #19 related to IDD, Changed ΘJA spec
from 28.51 to 18.7, Changed ΘJC spec from 5.91 to 4.5, Changed JTAG ID [31:29]
from 001 to 000.
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