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Cypress CY7C1393CV18, CY7C1992CV18, CY7C1394CV18 manual Package Diagram, Ball Fbga 13 x 15 x 1.4 mm

Models: CY7C1394CV18 CY7C1392CV18 CY7C1393CV18 CY7C1992CV18

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CY7C1392CV18, CY7C1992CV18

CY7C1393CV18, CY7C1394CV18

Package Diagram

Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180

15.00±0.10

TOP VIEW

PIN 1 CORNER

1.00

15.00±0.10	14.00

7.00

BOTTOM VIEW

PIN 1 CORNER

Ø0.05 M C

Ø0.25 M C A B

-0.06

Ø0.50 (165X)

+0.14

1.00

5.00

10.00

0.25 C

	B
0.53±0.05
0.36	C
0.36

13.00±0.10

		1.40MAX.

				0.15C

SEATING PLANE

0.35±0.06

B 13.00±0.10

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC

51-85180-*A

Document #: 001-07162 Rev. *C

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Cypress CY7C1393CV18, CY7C1992CV18, CY7C1394CV18, CY7C1392CV18 manual Package Diagram, Ball Fbga 13 x 15 x 1.4 mm

Contents

Configurations FeaturesFunctional Description Selection GuideDoff Logic Block Diagram CY7C1392CV18CLK Logic Block Diagram CY7C1394CV18 Logic Block Diagram CY7C1393CV18512K Array Gen Read Data Reg ControlBall Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1392CV18 2M x CY7C1992CV18 2M xCY7C1394CV18 512K x CY7C1393CV18 1M xSynchronous Read/Write input. When Pin DefinitionsPin Name Pin Description Power supply inputs for the outputs of the device Power supply inputs to the core of the deviceIs referenced with respect to TDO for JtagFunctional Overview Shows four DDR-II SIO used in an application Application ExampleWrite Cycle Descriptions Truth TableOperation CommentsWrite cycle description table for CY7C1394CV18 follows Write cycle description table for CY7C1992CV18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Input LOW Voltage Vref Document # 001-07162 Rev. *C AC Electrical CharacteristicsInput High Voltage Vref + Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitParameter Min Max Switching CharacteristicsHigh LOWDLL Timing Parameter Min Max Output TimesBurst Switching WaveformsOrdering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions